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[ARM] Cleanups for 4cc9bd2eaa
- Document the meaning for OP_SCALAR, OP_SD and add OP_DD. - Formatting cleanups - Remove now redundant code for making compare instructions operate on scalar values. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
parent
4cc9bd2eaa
commit
baf97ce6ed
3 changed files with 73 additions and 85 deletions
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@ -357,10 +357,14 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
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#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
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/*
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* A flag to tell vfp instruction type
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* A flag to tell vfp instruction type.
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* OP_SCALAR - this operation always operates in scalar mode
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* OP_SD - the instruction exceptionally writes to a single precision result.
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* OP_DD - the instruction exceptionally writes to a double precision result.
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*/
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#define OP_SCALAR (1 << 0)
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#define OP_SD (1 << 1)
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#define OP_DD (1 << 1)
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struct op {
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u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);
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@ -660,21 +660,21 @@ static u32 vfp_double_ftosiz(int dd, int unused, int dm, u32 fpscr)
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static struct op fops_ext[32] = {
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[FEXT_TO_IDX(FEXT_FCPY)] = {vfp_double_fcpy, 0},
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[FEXT_TO_IDX(FEXT_FABS)] = {vfp_double_fabs, 0},
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[FEXT_TO_IDX(FEXT_FNEG)] = {vfp_double_fneg, 0},
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[FEXT_TO_IDX(FEXT_FSQRT)] = {vfp_double_fsqrt, 0},
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[FEXT_TO_IDX(FEXT_FCMP)] = {vfp_double_fcmp, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPE)] = {vfp_double_fcmpe, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPZ)] = {vfp_double_fcmpz, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = {vfp_double_fcmpez, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCVT)] = {vfp_double_fcvts, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FUITO)] = {vfp_double_fuito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FSITO)] = {vfp_double_fsito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOUI)] = {vfp_double_ftoui, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = {vfp_double_ftouiz, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FTOSI)] = {vfp_double_ftosi, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = {vfp_double_ftosiz, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FCPY)] = { vfp_double_fcpy, 0 },
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[FEXT_TO_IDX(FEXT_FABS)] = { vfp_double_fabs, 0 },
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[FEXT_TO_IDX(FEXT_FNEG)] = { vfp_double_fneg, 0 },
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[FEXT_TO_IDX(FEXT_FSQRT)] = { vfp_double_fsqrt, 0 },
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[FEXT_TO_IDX(FEXT_FCMP)] = { vfp_double_fcmp, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCMPE)] = { vfp_double_fcmpe, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_double_fcmpz, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_double_fcmpez, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCVT)] = { vfp_double_fcvts, OP_SCALAR|OP_SD },
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[FEXT_TO_IDX(FEXT_FUITO)] = { vfp_double_fuito, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FSITO)] = { vfp_double_fsito, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_double_ftoui, OP_SCALAR|OP_SD },
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_double_ftouiz, OP_SCALAR|OP_SD },
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[FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_double_ftosi, OP_SCALAR|OP_SD },
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = { vfp_double_ftosiz, OP_SCALAR|OP_SD },
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};
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@ -1109,15 +1109,15 @@ static u32 vfp_double_fdiv(int dd, int dn, int dm, u32 fpscr)
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}
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static struct op fops[16] = {
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[FOP_TO_IDX(FOP_FMAC)] = {vfp_double_fmac, 0},
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[FOP_TO_IDX(FOP_FNMAC)] = {vfp_double_fnmac, 0},
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[FOP_TO_IDX(FOP_FMSC)] = {vfp_double_fmsc, 0},
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[FOP_TO_IDX(FOP_FNMSC)] = {vfp_double_fnmsc, 0},
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[FOP_TO_IDX(FOP_FMUL)] = {vfp_double_fmul, 0},
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[FOP_TO_IDX(FOP_FNMUL)] = {vfp_double_fnmul, 0},
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[FOP_TO_IDX(FOP_FADD)] = {vfp_double_fadd, 0},
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[FOP_TO_IDX(FOP_FSUB)] = {vfp_double_fsub, 0},
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[FOP_TO_IDX(FOP_FDIV)] = {vfp_double_fdiv, 0},
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[FOP_TO_IDX(FOP_FMAC)] = { vfp_double_fmac, 0 },
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[FOP_TO_IDX(FOP_FNMAC)] = { vfp_double_fnmac, 0 },
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[FOP_TO_IDX(FOP_FMSC)] = { vfp_double_fmsc, 0 },
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[FOP_TO_IDX(FOP_FNMSC)] = { vfp_double_fnmsc, 0 },
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[FOP_TO_IDX(FOP_FMUL)] = { vfp_double_fmul, 0 },
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[FOP_TO_IDX(FOP_FNMUL)] = { vfp_double_fnmul, 0 },
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[FOP_TO_IDX(FOP_FADD)] = { vfp_double_fadd, 0 },
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[FOP_TO_IDX(FOP_FSUB)] = { vfp_double_fsub, 0 },
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[FOP_TO_IDX(FOP_FDIV)] = { vfp_double_fdiv, 0 },
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};
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#define FREG_BANK(x) ((x) & 0x0c)
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@ -1136,6 +1136,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
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vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;
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fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
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/*
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* fcvtds takes an sN register number as destination, not dN.
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* It also always operates on scalars.
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@ -1162,19 +1163,17 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
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for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
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u32 except;
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char type;
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if (op == FOP_EXT && (fop->flags & OP_SD))
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pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n",
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type = fop->flags & OP_SD ? 's' : 'd';
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if (op == FOP_EXT)
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pr_debug("VFP: itr%d (%c%u) = op[%u] (d%u)\n",
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vecitr >> FPSCR_LENGTH_BIT,
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dest, dn, dm);
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else if (op == FOP_EXT)
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pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",
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vecitr >> FPSCR_LENGTH_BIT,
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dest, dn, dm);
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type, dest, dn, dm);
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else
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pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n",
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pr_debug("VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
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vecitr >> FPSCR_LENGTH_BIT,
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dest, dn, FOP_TO_IDX(op), dm);
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type, dest, dn, FOP_TO_IDX(op), dm);
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except = fop->fn(dest, dn, dm, fpscr);
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pr_debug("VFP: itr%d: exceptions=%08x\n",
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@ -1182,18 +1181,10 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
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exceptions |= except;
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/*
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* This ensures that comparisons only operate on scalars;
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* comparisons always return with one FPSCR status bit set.
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*/
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if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
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break;
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/*
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* CHECK: It appears to be undefined whether we stop when
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* we encounter an exception. We continue.
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*/
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dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);
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dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);
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if (FREG_BANK(dm) != 0)
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@ -703,21 +703,21 @@ static u32 vfp_single_ftosiz(int sd, int unused, s32 m, u32 fpscr)
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}
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static struct op fops_ext[32] = {
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[FEXT_TO_IDX(FEXT_FCPY)] = {vfp_single_fcpy, 0},
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[FEXT_TO_IDX(FEXT_FABS)] = {vfp_single_fabs, 0},
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[FEXT_TO_IDX(FEXT_FNEG)] = {vfp_single_fneg, 0},
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[FEXT_TO_IDX(FEXT_FSQRT)] = {vfp_single_fsqrt, 0},
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[FEXT_TO_IDX(FEXT_FCMP)] = {vfp_single_fcmp, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPE)] = {vfp_single_fcmpe, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPZ)] = {vfp_single_fcmpz, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = {vfp_single_fcmpez, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCVT)] = {vfp_single_fcvtd, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FUITO)] = {vfp_single_fuito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FSITO)] = {vfp_single_fsito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOUI)] = {vfp_single_ftoui, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = {vfp_single_ftouiz, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOSI)] = {vfp_single_ftosi, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = {vfp_single_ftosiz, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCPY)] = { vfp_single_fcpy, 0 },
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[FEXT_TO_IDX(FEXT_FABS)] = { vfp_single_fabs, 0 },
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[FEXT_TO_IDX(FEXT_FNEG)] = { vfp_single_fneg, 0 },
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[FEXT_TO_IDX(FEXT_FSQRT)] = { vfp_single_fsqrt, 0 },
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[FEXT_TO_IDX(FEXT_FCMP)] = { vfp_single_fcmp, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCMPE)] = { vfp_single_fcmpe, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_single_fcmpz, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_single_fcmpez, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FCVT)] = { vfp_single_fcvtd, OP_SCALAR|OP_DD },
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[FEXT_TO_IDX(FEXT_FUITO)] = { vfp_single_fuito, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FSITO)] = { vfp_single_fsito, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_single_ftoui, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_single_ftouiz, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_single_ftosi, OP_SCALAR },
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = { vfp_single_ftosiz, OP_SCALAR },
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};
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@ -1152,15 +1152,15 @@ static u32 vfp_single_fdiv(int sd, int sn, s32 m, u32 fpscr)
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}
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static struct op fops[16] = {
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[FOP_TO_IDX(FOP_FMAC)] = {vfp_single_fmac, 0},
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[FOP_TO_IDX(FOP_FNMAC)] = {vfp_single_fnmac, 0},
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[FOP_TO_IDX(FOP_FMSC)] = {vfp_single_fmsc, 0},
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[FOP_TO_IDX(FOP_FNMSC)] = {vfp_single_fnmsc, 0},
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[FOP_TO_IDX(FOP_FMUL)] = {vfp_single_fmul, 0},
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[FOP_TO_IDX(FOP_FNMUL)] = {vfp_single_fnmul, 0},
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[FOP_TO_IDX(FOP_FADD)] = {vfp_single_fadd, 0},
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[FOP_TO_IDX(FOP_FSUB)] = {vfp_single_fsub, 0},
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[FOP_TO_IDX(FOP_FDIV)] = {vfp_single_fdiv, 0},
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[FOP_TO_IDX(FOP_FMAC)] = { vfp_single_fmac, 0 },
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[FOP_TO_IDX(FOP_FNMAC)] = { vfp_single_fnmac, 0 },
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[FOP_TO_IDX(FOP_FMSC)] = { vfp_single_fmsc, 0 },
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[FOP_TO_IDX(FOP_FNMSC)] = { vfp_single_fnmsc, 0 },
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[FOP_TO_IDX(FOP_FMUL)] = { vfp_single_fmul, 0 },
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[FOP_TO_IDX(FOP_FNMUL)] = { vfp_single_fnmul, 0 },
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[FOP_TO_IDX(FOP_FADD)] = { vfp_single_fadd, 0 },
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[FOP_TO_IDX(FOP_FSUB)] = { vfp_single_fsub, 0 },
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[FOP_TO_IDX(FOP_FDIV)] = { vfp_single_fdiv, 0 },
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};
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#define FREG_BANK(x) ((x) & 0x18)
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@ -1179,22 +1179,23 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
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vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);
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fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
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/*
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* fcvtsd takes a dN register number as destination, not sN.
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* Technically, if bit 0 of dd is set, this is an invalid
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* instruction. However, we ignore this for efficiency.
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* It also only operates on scalars.
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*/
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if (fop->flags & OP_SD) {
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if (fop->flags & OP_DD)
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dest = vfp_get_dd(inst);
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} else
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else
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dest = vfp_get_sd(inst);
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/*
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* If destination bank is zero, vector length is always '1'.
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* ARM DDI0100F C5.1.3, C5.3.2.
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*/
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if ((fop->flags & OP_SCALAR) || (FREG_BANK(dest) == 0))
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if ((fop->flags & OP_SCALAR) || FREG_BANK(dest) == 0)
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veclen = 0;
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else
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veclen = fpscr & FPSCR_LENGTH_MASK;
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@ -1208,16 +1209,16 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
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for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
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s32 m = vfp_get_float(sm);
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u32 except;
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char type;
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if (op == FOP_EXT && (fop->flags & OP_SD))
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pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n",
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vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
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else if (op == FOP_EXT)
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pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n",
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vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
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type = fop->flags & OP_DD ? 'd' : 's';
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if (op == FOP_EXT)
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pr_debug("VFP: itr%d (%c%u) = op[%u] (s%u=%08x)\n",
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vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,
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sm, m);
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else
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pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n",
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vecitr >> FPSCR_LENGTH_BIT, dest, sn,
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pr_debug("VFP: itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)\n",
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vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,
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FOP_TO_IDX(op), sm, m);
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except = fop->fn(dest, sn, m, fpscr);
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@ -1226,18 +1227,10 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
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exceptions |= except;
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/*
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* This ensures that comparisons only operate on scalars;
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* comparisons always return with one FPSCR status bit set.
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*/
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if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
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break;
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/*
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* CHECK: It appears to be undefined whether we stop when
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* we encounter an exception. We continue.
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*/
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dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7);
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sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7);
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if (FREG_BANK(sm) != 0)
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