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Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
TWL4030: fix clk API usage
[ARM] 5364/1: allow flush_ioremap_region() to be used from modules
[ARM] w90x900: fix build errors and warnings
[ARM] i.MX add missing include
[ARM] i.MX: fix breakage from commit 278892736e
[ARM] i.MX: remove LCDC controller register definitions from imx-regs.h
This commit is contained in:
Linus Torvalds
commit
b9a0d06a35
7 changed files with 10 additions and 115 deletions
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@ -23,7 +23,7 @@
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/imx-regs.h>
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#include <mach/hardware.h>
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/*
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* Very simple approach: We can't disable clocks, so we do
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@ -245,11 +245,11 @@ void __init imx_set_mmc_info(struct imxmmc_platform_data *info)
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imx_mmc_device.dev.platform_data = info;
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}
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static struct imxfb_mach_info imx_fb_info;
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static struct imx_fb_platform_data imx_fb_info;
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void __init set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info)
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void __init set_imx_fb_info(struct imx_fb_platform_data *hard_imx_fb_info)
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{
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memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imxfb_mach_info));
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memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imx_fb_platform_data));
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}
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static struct resource imxfb_resources[] = {
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@ -373,110 +373,4 @@
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#define TSTAT_CAPT (1<<1)
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#define TSTAT_COMP (1<<0)
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/*
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* LCD Controller
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*/
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#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
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#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
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#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
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#define SIZE_YMAX(y) ( (y) & 0x1ff )
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#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
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#define VPW_VPW(x) ( (x) & 0x3ff )
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#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
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#define CPOS_CC1 (1<<31)
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#define CPOS_CC0 (1<<30)
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#define CPOS_OP (1<<28)
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#define CPOS_CXP(x) (((x) & 3ff) << 16)
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#define CPOS_CYP(y) ((y) & 0x1ff)
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#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
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#define LCWHB_BK_EN (1<<31)
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#define LCWHB_CW(w) (((w) & 0x1f) << 24)
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#define LCWHB_CH(h) (((h) & 0x1f) << 16)
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#define LCWHB_BD(x) ((x) & 0xff)
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#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
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#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
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#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
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#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
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#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
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#define PCR_TFT (1<<31)
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#define PCR_COLOR (1<<30)
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#define PCR_PBSIZ_1 (0<<28)
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#define PCR_PBSIZ_2 (1<<28)
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#define PCR_PBSIZ_4 (2<<28)
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#define PCR_PBSIZ_8 (3<<28)
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#define PCR_BPIX_1 (0<<25)
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#define PCR_BPIX_2 (1<<25)
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#define PCR_BPIX_4 (2<<25)
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#define PCR_BPIX_8 (3<<25)
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#define PCR_BPIX_12 (4<<25)
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#define PCR_BPIX_16 (4<<25)
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#define PCR_PIXPOL (1<<24)
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#define PCR_FLMPOL (1<<23)
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#define PCR_LPPOL (1<<22)
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#define PCR_CLKPOL (1<<21)
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#define PCR_OEPOL (1<<20)
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#define PCR_SCLKIDLE (1<<19)
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#define PCR_END_SEL (1<<18)
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#define PCR_END_BYTE_SWAP (1<<17)
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#define PCR_REV_VS (1<<16)
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#define PCR_ACD_SEL (1<<15)
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#define PCR_ACD(x) (((x) & 0x7f) << 8)
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#define PCR_SCLK_SEL (1<<7)
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#define PCR_SHARP (1<<6)
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#define PCR_PCD(x) ((x) & 0x3f)
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#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
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#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
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#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
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#define HCR_H_WAIT_2(x) ((x) & 0xff)
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#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
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#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
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#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
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#define VCR_V_WAIT_2(x) ((x) & 0xff)
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#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
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#define POS_POS(x) ((x) & 1f)
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#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
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#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
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#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
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#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
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#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
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#define LSCR1_GRAY1(x) (((x) & 0xf))
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#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
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#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
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#define PWMR_LDMSK (1<<15)
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#define PWMR_SCR1 (1<<10)
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#define PWMR_SCR0 (1<<9)
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#define PWMR_CC_EN (1<<8)
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#define PWMR_PW(x) ((x) & 0xff)
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#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
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#define DMACR_BURST (1<<31)
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#define DMACR_HM(x) (((x) & 0xf) << 16)
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#define DMACR_TM(x) ((x) &0xf)
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#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
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#define RMCR_LCDC_EN (1<<1)
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#define RMCR_SELF_REF (1<<0)
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#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
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#define LCDICR_INT_SYN (1<<2)
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#define LCDICR_INT_CON (1)
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#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
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#define LCDISR_UDR_ERR (1<<3)
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#define LCDISR_ERR_RES (1<<2)
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#define LCDISR_EOF (1<<1)
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#define LCDISR_BOF (1<<0)
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#endif // _IMX_REGS_H
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@ -29,6 +29,7 @@
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#include <asm/mach-types.h>
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#include <mach/regs-serial.h>
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#include <mach/map.h>
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#include "cpu.h"
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@ -28,7 +28,6 @@
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <mach/system.h>
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#include <mach/map.h>
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#include <mach/regs-timer.h>
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@ -27,6 +27,7 @@ EXPORT_SYMBOL(__cpuc_flush_kern_all);
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EXPORT_SYMBOL(__cpuc_flush_user_all);
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EXPORT_SYMBOL(__cpuc_flush_user_range);
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EXPORT_SYMBOL(__cpuc_coherent_kern_range);
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EXPORT_SYMBOL(dmac_inv_range); /* because of flush_ioremap_region() */
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#else
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EXPORT_SYMBOL(cpu_cache);
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#endif
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@ -649,7 +649,7 @@ static inline int __init unprotect_pm_master(void)
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return e;
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}
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static void __init clocks_init(void)
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static void __init clocks_init(struct device *dev)
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{
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int e = 0;
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struct clk *osc;
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@ -658,9 +658,9 @@ static void __init clocks_init(void)
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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if (cpu_is_omap2430())
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osc = clk_get(NULL, "osc_ck");
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osc = clk_get(dev, "osc_ck");
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else
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osc = clk_get(NULL, "osc_sys_ck");
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osc = clk_get(dev, "osc_sys_ck");
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if (IS_ERR(osc)) {
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printk(KERN_WARNING "Skipping twl4030 internal clock init and "
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@ -776,7 +776,7 @@ twl4030_probe(struct i2c_client *client, const struct i2c_device_id *id)
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inuse = true;
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/* setup clock framework */
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clocks_init();
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clocks_init(&client->dev);
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/* Maybe init the T2 Interrupt subsystem */
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if (client->irq
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