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[POWERPC] Refactor DCR code
Previously, DCR support was configured at compile time to either use MMIO or native dcr instructions. Although this works for most platforms, it fails on FPGA platforms: 1) Systems may include more than one DCR bus. 2) Systems may be native DCR capable and still use memory mapped DCR interface. This patch provides runtime support based on the device trees for the case where CONFIG_PPC_DCR_MMIO and CONFIG_PPC_DCR_NATIVE are both selected. Previously, this was a poorly defined configuration, which happened to provide NATIVE support. The runtime selection is made based on the dcr-controller having a 'dcr-access-method' attribute in the device tree. If only one of the above options is selected, then the code uses #defines to select only the used code in order to avoid introducing overhead in existing usage. Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Stephen Neuendorffer
Josh Boyer
parent
acf464817d
commit
b786af117b
5 changed files with 231 additions and 47 deletions
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@ -23,6 +23,105 @@
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#include <asm/prom.h>
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#include <asm/dcr.h>
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static struct device_node *find_dcr_parent(struct device_node *node)
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{
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struct device_node *par, *tmp;
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const u32 *p;
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for (par = of_node_get(node); par;) {
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if (of_get_property(par, "dcr-controller", NULL))
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break;
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p = of_get_property(par, "dcr-parent", NULL);
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tmp = par;
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if (p == NULL)
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par = of_get_parent(par);
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else
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par = of_find_node_by_phandle(*p);
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of_node_put(tmp);
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}
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return par;
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}
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#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
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bool dcr_map_ok_generic(dcr_host_t host)
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{
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if (host.type == DCR_HOST_NATIVE)
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return dcr_map_ok_native(host.host.native);
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else if (host.type == DCR_HOST_MMIO)
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return dcr_map_ok_mmio(host.host.mmio);
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else
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return 0;
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}
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EXPORT_SYMBOL_GPL(dcr_map_ok_generic);
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dcr_host_t dcr_map_generic(struct device_node *dev,
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unsigned int dcr_n,
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unsigned int dcr_c)
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{
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dcr_host_t host;
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struct device_node *dp;
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const char *prop;
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host.type = DCR_HOST_INVALID;
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dp = find_dcr_parent(dev);
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if (dp == NULL)
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return host;
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prop = of_get_property(dp, "dcr-access-method", NULL);
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pr_debug("dcr_map_generic(dcr-access-method = %s)\n", prop);
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if (!strcmp(prop, "native")) {
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host.type = DCR_HOST_NATIVE;
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host.host.native = dcr_map_native(dev, dcr_n, dcr_c);
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} else if (!strcmp(prop, "mmio")) {
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host.type = DCR_HOST_MMIO;
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host.host.mmio = dcr_map_mmio(dev, dcr_n, dcr_c);
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}
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of_node_put(dp);
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return host;
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}
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EXPORT_SYMBOL_GPL(dcr_map_generic);
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void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c)
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{
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if (host.type == DCR_HOST_NATIVE)
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dcr_unmap_native(host.host.native, dcr_c);
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else if (host.type == DCR_HOST_MMIO)
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dcr_unmap_mmio(host.host.mmio, dcr_c);
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else /* host.type == DCR_HOST_INVALID */
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WARN_ON(true);
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}
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EXPORT_SYMBOL_GPL(dcr_unmap_generic);
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u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n)
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{
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if (host.type == DCR_HOST_NATIVE)
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return dcr_read_native(host.host.native, dcr_n);
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else if (host.type == DCR_HOST_MMIO)
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return dcr_read_mmio(host.host.mmio, dcr_n);
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else /* host.type == DCR_HOST_INVALID */
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WARN_ON(true);
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return 0;
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}
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EXPORT_SYMBOL_GPL(dcr_read_generic);
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void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value)
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{
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if (host.type == DCR_HOST_NATIVE)
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dcr_write_native(host.host.native, dcr_n, value);
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else if (host.type == DCR_HOST_MMIO)
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dcr_write_mmio(host.host.mmio, dcr_n, value);
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else /* host.type == DCR_HOST_INVALID */
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WARN_ON(true);
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}
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EXPORT_SYMBOL_GPL(dcr_write_generic);
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#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
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unsigned int dcr_resource_start(struct device_node *np, unsigned int index)
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{
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unsigned int ds;
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@ -47,26 +146,7 @@ unsigned int dcr_resource_len(struct device_node *np, unsigned int index)
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}
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EXPORT_SYMBOL_GPL(dcr_resource_len);
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#ifndef CONFIG_PPC_DCR_NATIVE
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static struct device_node * find_dcr_parent(struct device_node * node)
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{
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struct device_node *par, *tmp;
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const u32 *p;
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for (par = of_node_get(node); par;) {
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if (of_get_property(par, "dcr-controller", NULL))
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break;
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p = of_get_property(par, "dcr-parent", NULL);
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tmp = par;
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if (p == NULL)
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par = of_get_parent(par);
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else
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par = of_find_node_by_phandle(*p);
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of_node_put(tmp);
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}
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return par;
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}
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#ifdef CONFIG_PPC_DCR_MMIO
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u64 of_translate_dcr_address(struct device_node *dev,
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unsigned int dcr_n,
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@ -75,7 +155,7 @@ u64 of_translate_dcr_address(struct device_node *dev,
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struct device_node *dp;
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const u32 *p;
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unsigned int stride;
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u64 ret;
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u64 ret = OF_BAD_ADDR;
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dp = find_dcr_parent(dev);
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if (dp == NULL)
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@ -90,7 +170,7 @@ u64 of_translate_dcr_address(struct device_node *dev,
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if (p == NULL)
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p = of_get_property(dp, "dcr-mmio-space", NULL);
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if (p == NULL)
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return OF_BAD_ADDR;
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goto done;
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/* Maybe could do some better range checking here */
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ret = of_translate_address(dp, p);
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@ -98,21 +178,25 @@ u64 of_translate_dcr_address(struct device_node *dev,
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ret += (u64)(stride) * (u64)dcr_n;
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if (out_stride)
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*out_stride = stride;
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done:
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of_node_put(dp);
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return ret;
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}
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dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
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unsigned int dcr_c)
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dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
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unsigned int dcr_n,
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unsigned int dcr_c)
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{
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dcr_host_t ret = { .token = NULL, .stride = 0, .base = dcr_n };
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dcr_host_mmio_t ret = { .token = NULL, .stride = 0, .base = dcr_n };
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u64 addr;
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pr_debug("dcr_map(%s, 0x%x, 0x%x)\n",
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dev->full_name, dcr_n, dcr_c);
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addr = of_translate_dcr_address(dev, dcr_n, &ret.stride);
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pr_debug("translates to addr: 0x%lx, stride: 0x%x\n",
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addr, ret.stride);
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pr_debug("translates to addr: 0x%llx, stride: 0x%x\n",
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(unsigned long long) addr, ret.stride);
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if (addr == OF_BAD_ADDR)
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return ret;
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pr_debug("mapping 0x%x bytes\n", dcr_c * ret.stride);
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@ -124,11 +208,11 @@ dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
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ret.token -= dcr_n * ret.stride;
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return ret;
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}
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EXPORT_SYMBOL_GPL(dcr_map);
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EXPORT_SYMBOL_GPL(dcr_map_mmio);
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void dcr_unmap(dcr_host_t host, unsigned int dcr_c)
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void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c)
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{
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dcr_host_t h = host;
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dcr_host_mmio_t h = host;
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if (h.token == NULL)
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return;
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@ -136,7 +220,11 @@ void dcr_unmap(dcr_host_t host, unsigned int dcr_c)
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iounmap(h.token);
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h.token = NULL;
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}
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EXPORT_SYMBOL_GPL(dcr_unmap);
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#else /* defined(CONFIG_PPC_DCR_NATIVE) */
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EXPORT_SYMBOL_GPL(dcr_unmap_mmio);
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#endif /* defined(CONFIG_PPC_DCR_MMIO) */
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#ifdef CONFIG_PPC_DCR_NATIVE
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DEFINE_SPINLOCK(dcr_ind_lock);
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#endif /* !defined(CONFIG_PPC_DCR_NATIVE) */
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#endif /* defined(CONFIG_PPC_DCR_NATIVE) */
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49
include/asm-powerpc/dcr-generic.h
Normal file
49
include/asm-powerpc/dcr-generic.h
Normal file
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@ -0,0 +1,49 @@
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/*
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* (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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* the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_POWERPC_DCR_GENERIC_H
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#define _ASM_POWERPC_DCR_GENERIC_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID};
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typedef struct {
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enum host_type_t type;
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union {
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dcr_host_mmio_t mmio;
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dcr_host_native_t native;
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} host;
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} dcr_host_t;
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extern bool dcr_map_ok_generic(dcr_host_t host);
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extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n,
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unsigned int dcr_c);
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extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
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extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
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extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value);
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_DCR_GENERIC_H */
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@ -27,20 +27,26 @@ typedef struct {
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void __iomem *token;
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unsigned int stride;
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unsigned int base;
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} dcr_host_t;
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} dcr_host_mmio_t;
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#define DCR_MAP_OK(host) ((host).token != NULL)
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static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
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{
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return host.token != NULL;
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}
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extern dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
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unsigned int dcr_c);
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extern void dcr_unmap(dcr_host_t host, unsigned int dcr_c);
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extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
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unsigned int dcr_n,
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unsigned int dcr_c);
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extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c);
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static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
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static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n)
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{
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return in_be32(host.token + ((host.base + dcr_n) * host.stride));
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}
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static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value)
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static inline void dcr_write_mmio(dcr_host_mmio_t host,
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unsigned int dcr_n,
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u32 value)
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{
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out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
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}
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@ -26,14 +26,18 @@
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typedef struct {
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unsigned int base;
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} dcr_host_t;
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} dcr_host_native_t;
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#define DCR_MAP_OK(host) (1)
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static inline bool dcr_map_ok_native(dcr_host_native_t host)
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{
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return 1;
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}
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#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) })
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#define dcr_unmap(host, dcr_c) do {} while (0)
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#define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base)
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#define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
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#define dcr_map_native(dev, dcr_n, dcr_c) \
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((dcr_host_native_t){ .base = (dcr_n) })
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#define dcr_unmap_native(host, dcr_c) do {} while (0)
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#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
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#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
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/* Device Control Registers */
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void __mtdcr(int reg, unsigned int val);
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@ -20,14 +20,50 @@
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#ifndef _ASM_POWERPC_DCR_H
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#define _ASM_POWERPC_DCR_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_PPC_DCR
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#ifdef CONFIG_PPC_DCR_NATIVE
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#include <asm/dcr-native.h>
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#else
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#endif
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#ifdef CONFIG_PPC_DCR_MMIO
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#include <asm/dcr-mmio.h>
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#endif
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/* Indirection layer for providing both NATIVE and MMIO support. */
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#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
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#include <asm/dcr-generic.h>
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#define DCR_MAP_OK(host) dcr_map_ok_generic(host)
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#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
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#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
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#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
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#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
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#else
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#ifdef CONFIG_PPC_DCR_NATIVE
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typedef dcr_host_native_t dcr_host_t;
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#define DCR_MAP_OK(host) dcr_map_ok_native(host)
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#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
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#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
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#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
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#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
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#else
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typedef dcr_host_mmio_t dcr_host_t;
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#define DCR_MAP_OK(host) dcr_map_ok_mmio(host)
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#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
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#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
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#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
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#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
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#endif
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#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
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/*
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* On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
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* base from the device-tree
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@ -41,5 +77,6 @@ extern unsigned int dcr_resource_len(struct device_node *np,
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#endif /* CONFIG_PPC_MERGE */
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#endif /* CONFIG_PPC_DCR */
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_DCR_H */
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