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amd64_edac: add MCA error types
Borislav: - cleanup comments Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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Doug Thompson
Borislav Petkov
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eb919690be
commit
b52401cece
1 changed files with 161 additions and 0 deletions
161
drivers/edac/amd64_edac_err_types.c
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161
drivers/edac/amd64_edac_err_types.c
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#include "amd64_edac.h"
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/*
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* See F2x80 for K8 and F2x[1,0]80 for Fam10 and later. The table below is only
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* for DDR2 DRAM mapping.
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*/
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u32 revf_quad_ddr2_shift[] = {
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0, /* 0000b NULL DIMM (128mb) */
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28, /* 0001b 256mb */
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29, /* 0010b 512mb */
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29, /* 0011b 512mb */
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29, /* 0100b 512mb */
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30, /* 0101b 1gb */
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30, /* 0110b 1gb */
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31, /* 0111b 2gb */
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31, /* 1000b 2gb */
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32, /* 1001b 4gb */
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32, /* 1010b 4gb */
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33, /* 1011b 8gb */
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0, /* 1100b future */
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0, /* 1101b future */
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0, /* 1110b future */
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0 /* 1111b future */
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};
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/*
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* Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
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* bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
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* or higher value'.
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*
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*FIXME: Produce a better mapping/linearisation.
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*/
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struct scrubrate scrubrates[] = {
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{ 0x01, 1600000000UL},
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{ 0x02, 800000000UL},
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{ 0x03, 400000000UL},
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{ 0x04, 200000000UL},
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{ 0x05, 100000000UL},
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{ 0x06, 50000000UL},
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{ 0x07, 25000000UL},
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{ 0x08, 12284069UL},
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{ 0x09, 6274509UL},
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{ 0x0A, 3121951UL},
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{ 0x0B, 1560975UL},
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{ 0x0C, 781440UL},
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{ 0x0D, 390720UL},
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{ 0x0E, 195300UL},
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{ 0x0F, 97650UL},
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{ 0x10, 48854UL},
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{ 0x11, 24427UL},
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{ 0x12, 12213UL},
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{ 0x13, 6101UL},
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{ 0x14, 3051UL},
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{ 0x15, 1523UL},
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{ 0x16, 761UL},
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{ 0x00, 0UL}, /* scrubbing off */
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};
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/*
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* string representation for the different MCA reported error types, see F3x48
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* or MSR0000_0411.
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*/
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const char *tt_msgs[] = { /* transaction type */
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"instruction",
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"data",
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"generic",
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"reserved"
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};
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const char *ll_msgs[] = { /* cache level */
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"L0",
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"L1",
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"L2",
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"L3/generic"
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};
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const char *rrrr_msgs[] = {
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"generic",
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"generic read",
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"generic write",
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"data read",
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"data write",
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"inst fetch",
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"prefetch",
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"evict",
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"snoop",
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"reserved RRRR= 9",
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"reserved RRRR= 10",
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"reserved RRRR= 11",
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"reserved RRRR= 12",
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"reserved RRRR= 13",
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"reserved RRRR= 14",
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"reserved RRRR= 15"
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};
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const char *pp_msgs[] = { /* participating processor */
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"local node originated (SRC)",
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"local node responded to request (RES)",
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"local node observed as 3rd party (OBS)",
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"generic"
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};
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const char *to_msgs[] = {
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"no timeout",
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"timed out"
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};
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const char *ii_msgs[] = { /* memory or i/o */
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"mem access",
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"reserved",
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"i/o access",
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"generic"
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};
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/* Map the 5 bits of Extended Error code to the string table. */
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const char *ext_msgs[] = { /* extended error */
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"K8 ECC error/F10 reserved", /* 0_0000b */
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"CRC error", /* 0_0001b */
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"sync error", /* 0_0010b */
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"mst abort", /* 0_0011b */
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"tgt abort", /* 0_0100b */
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"GART error", /* 0_0101b */
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"RMW error", /* 0_0110b */
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"Wdog timer error", /* 0_0111b */
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"F10-ECC/K8-Chipkill error", /* 0_1000b */
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"DEV Error", /* 0_1001b */
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"Link Data error", /* 0_1010b */
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"Link or L3 Protocol error", /* 0_1011b */
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"NB Array error", /* 0_1100b */
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"DRAM Parity error", /* 0_1101b */
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"Link Retry/GART Table Walk/DEV Table Walk error", /* 0_1110b */
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"Res 0x0ff error", /* 0_1111b */
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"Res 0x100 error", /* 1_0000b */
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"Res 0x101 error", /* 1_0001b */
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"Res 0x102 error", /* 1_0010b */
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"Res 0x103 error", /* 1_0011b */
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"Res 0x104 error", /* 1_0100b */
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"Res 0x105 error", /* 1_0101b */
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"Res 0x106 error", /* 1_0110b */
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"Res 0x107 error", /* 1_0111b */
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"Res 0x108 error", /* 1_1000b */
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"Res 0x109 error", /* 1_1001b */
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"Res 0x10A error", /* 1_1010b */
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"Res 0x10B error", /* 1_1011b */
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"L3 Cache Data error", /* 1_1100b */
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"L3 CacheTag error", /* 1_1101b */
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"L3 Cache LRU error", /* 1_1110b */
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"Res 0x1FF error" /* 1_1111b */
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};
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const char *htlink_msgs[] = {
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"none",
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"1",
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"2",
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"1 2",
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"3",
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"1 3",
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"2 3",
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"1 2 3"
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};
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