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Staging: et131x: Kill MAC_IF_CTRL typedefs
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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2 changed files with 29 additions and 50 deletions
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@ -1451,49 +1451,25 @@ typedef struct _RXMAC_t { /* Location: */
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/*
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* structure for Interface Control reg in mac address map.
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* located at address 0x5038
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*
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* 31: reset if module
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* 30-28: reserved
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* 27: tbi mode
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* 26: ghd mode
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* 25: lhd mode
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* 24: phy mode
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* 23: reset per mii
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* 22-17: reserved
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* 16: speed
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* 15: reset pe100x
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* 14-11: reserved
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* 10: force quiet
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* 9: no cipher
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* 8: disable link fail
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* 7: reset gpsi
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* 6-1: reserved
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* 0: enable jabber protection
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*/
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typedef union _MAC_IF_CTRL_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 reset_if_module:1; /* bit 31 */
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u32 reserved4:3; /* bit 28-30 */
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u32 tbi_mode:1; /* bit 27 */
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u32 ghd_mode:1; /* bit 26 */
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u32 lhd_mode:1; /* bit 25 */
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u32 phy_mode:1; /* bit 24 */
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u32 reset_per_mii:1; /* bit 23 */
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u32 reserved3:6; /* bits 17-22 */
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u32 speed:1; /* bit 16 */
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u32 reset_pe100x:1; /* bit 15 */
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u32 reserved2:4; /* bits 11-14 */
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u32 force_quiet:1; /* bit 10 */
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u32 no_cipher:1; /* bit 9 */
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u32 disable_link_fail:1; /* bit 8 */
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u32 reset_gpsi:1; /* bit 7 */
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u32 reserved1:6; /* bits 1-6 */
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u32 enab_jab_protect:1; /* bit 0 */
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#else
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u32 enab_jab_protect:1; /* bit 0 */
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u32 reserved1:6; /* bits 1-6 */
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u32 reset_gpsi:1; /* bit 7 */
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u32 disable_link_fail:1; /* bit 8 */
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u32 no_cipher:1; /* bit 9 */
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u32 force_quiet:1; /* bit 10 */
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u32 reserved2:4; /* bits 11-14 */
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u32 reset_pe100x:1; /* bit 15 */
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u32 speed:1; /* bit 16 */
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u32 reserved3:6; /* bits 17-22 */
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u32 reset_per_mii:1; /* bit 23 */
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u32 phy_mode:1; /* bit 24 */
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u32 lhd_mode:1; /* bit 25 */
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u32 ghd_mode:1; /* bit 26 */
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u32 tbi_mode:1; /* bit 27 */
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u32 reserved4:3; /* bit 28-30 */
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u32 reset_if_module:1; /* bit 31 */
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#endif
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} bits;
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} MAC_IF_CTRL_t, *PMAC_IF_CTRL_t;
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/*
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* structure for Interface Status reg in mac address map.
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@ -1588,7 +1564,7 @@ typedef struct _MAC_t { /* Location: */
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u32 mii_mgmt_ctrl; /* 0x502C */
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u32 mii_mgmt_stat; /* 0x5030 */
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u32 mii_mgmt_indicator; /* 0x5034 */
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MAC_IF_CTRL_t if_ctrl; /* 0x5038 */
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u32 if_ctrl; /* 0x5038 */
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MAC_IF_STAT_t if_stat; /* 0x503C */
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MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
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MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
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@ -118,7 +118,7 @@ void ConfigMACRegs1(struct et131x_adapter *etdev)
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writel(0x00A1F037, &pMac->hfdp);
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/* Next lets configure the MAC Interface Control register */
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writel(0, &pMac->if_ctrl.value);
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writel(0, &pMac->if_ctrl);
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/* Let's move on to setting up the mii management configuration */
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writel(0x07, &pMac->mii_mgmt_cfg); /* Clock reset 0x7 */
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@ -162,22 +162,23 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
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struct _MAC_t __iomem *pMac = &etdev->regs->mac;
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u32 cfg1;
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u32 cfg2;
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MAC_IF_CTRL_t ifctrl;
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u32 ifctrl;
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TXMAC_CTL_t ctl;
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ctl.value = readl(&etdev->regs->txmac.ctl.value);
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cfg1 = readl(&pMac->cfg1);
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cfg2 = readl(&pMac->cfg2);
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ifctrl.value = readl(&pMac->if_ctrl.value);
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ifctrl = readl(&pMac->if_ctrl);
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/* Set up the if mode bits */
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cfg2 &= ~0x300;
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if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
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cfg2 |= 0x200;
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ifctrl.bits.phy_mode = 0x0;
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/* Phy mode bit */
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ifctrl &= ~(1 << 24);
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} else {
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cfg2 |= 0x100;
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ifctrl.bits.phy_mode = 0x1;
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ifctrl |= (1 << 24);
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}
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/* We need to enable Rx/Tx */
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@ -198,9 +199,11 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
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if (etdev->duplex_mode)
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cfg2 |= 0x01;
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ifctrl.bits.ghd_mode = !etdev->duplex_mode;
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ifctrl &= ~(1 << 26);
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if (!etdev->duplex_mode)
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ifctrl |= (1<<26); /* Enable ghd */
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writel(ifctrl.value, &pMac->if_ctrl.value);
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writel(ifctrl, &pMac->if_ctrl);
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writel(cfg2, &pMac->cfg2);
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do {
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