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https://github.com/adulau/aha.git
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edac: i5100 clean controller to channel terms
The i5100 driver uses the word controller instead of channel in a lot of places, this is simply a cleanup of the patch. Signed-off-by: Nils Carlson <nils.carlson@ludd.ltu.se> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Nils Carlson
Linus Torvalds
parent
417e315247
commit
b18dfd05f9
1 changed files with 55 additions and 55 deletions
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@ -265,42 +265,42 @@ static inline u32 i5100_recmemb_ras(u32 a)
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}
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/* some generic limits */
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#define I5100_MAX_RANKS_PER_CTLR 6
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#define I5100_MAX_CTLRS 2
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#define I5100_MAX_RANKS_PER_CHAN 6
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#define I5100_CHANNELS 2
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#define I5100_MAX_RANKS_PER_DIMM 4
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#define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
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#define I5100_MAX_DIMM_SLOTS_PER_CTLR 4
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#define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
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#define I5100_MAX_RANK_INTERLEAVE 4
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#define I5100_MAX_DMIRS 5
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struct i5100_priv {
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/* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
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int dimm_numrank[I5100_MAX_CTLRS][I5100_MAX_DIMM_SLOTS_PER_CTLR];
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int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
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/*
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* mainboard chip select map -- maps i5100 chip selects to
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* DIMM slot chip selects. In the case of only 4 ranks per
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* controller, the mapping is fairly obvious but not unique.
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* we map -1 -> NC and assume both controllers use the same
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* channel, the mapping is fairly obvious but not unique.
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* we map -1 -> NC and assume both channels use the same
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* map...
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*
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*/
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int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CTLR][I5100_MAX_RANKS_PER_DIMM];
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int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
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/* memory interleave range */
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struct {
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u64 limit;
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unsigned way[2];
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} mir[I5100_MAX_CTLRS];
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} mir[I5100_CHANNELS];
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/* adjusted memory interleave range register */
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unsigned amir[I5100_MAX_CTLRS];
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unsigned amir[I5100_CHANNELS];
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/* dimm interleave range */
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struct {
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unsigned rank[I5100_MAX_RANK_INTERLEAVE];
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u64 limit;
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} dmir[I5100_MAX_CTLRS][I5100_MAX_DMIRS];
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} dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
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/* memory technology registers... */
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struct {
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@ -310,30 +310,30 @@ struct i5100_priv {
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unsigned numbank; /* 2 or 3 lines */
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unsigned numrow; /* 13 .. 16 lines */
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unsigned numcol; /* 11 .. 12 lines */
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} mtr[I5100_MAX_CTLRS][I5100_MAX_RANKS_PER_CTLR];
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} mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
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u64 tolm; /* top of low memory in bytes */
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unsigned ranksperctlr; /* number of ranks per controller */
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unsigned ranksperchan; /* number of ranks per channel */
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struct pci_dev *mc; /* device 16 func 1 */
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struct pci_dev *ch0mm; /* device 21 func 0 */
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struct pci_dev *ch1mm; /* device 22 func 0 */
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};
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/* map a rank/ctlr to a slot number on the mainboard */
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/* map a rank/chan to a slot number on the mainboard */
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static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
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int ctlr, int rank)
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int chan, int rank)
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{
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const struct i5100_priv *priv = mci->pvt_info;
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int i;
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for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CTLR; i++) {
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for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
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int j;
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const int numrank = priv->dimm_numrank[ctlr][i];
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const int numrank = priv->dimm_numrank[chan][i];
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for (j = 0; j < numrank; j++)
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if (priv->dimm_csmap[i][j] == rank)
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return i * 2 + ctlr;
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return i * 2 + chan;
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}
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return -1;
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@ -374,32 +374,32 @@ static const char *i5100_err_msg(unsigned err)
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return "none";
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}
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/* convert csrow index into a rank (per controller -- 0..5) */
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/* convert csrow index into a rank (per channel -- 0..5) */
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static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
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{
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const struct i5100_priv *priv = mci->pvt_info;
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return csrow % priv->ranksperctlr;
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return csrow % priv->ranksperchan;
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}
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/* convert csrow index into a controller (0..1) */
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static int i5100_csrow_to_cntlr(const struct mem_ctl_info *mci, int csrow)
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/* convert csrow index into a channel (0..1) */
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static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
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{
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const struct i5100_priv *priv = mci->pvt_info;
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return csrow / priv->ranksperctlr;
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return csrow / priv->ranksperchan;
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}
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static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci,
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int ctlr, int rank)
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int chan, int rank)
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{
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const struct i5100_priv *priv = mci->pvt_info;
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return ctlr * priv->ranksperctlr + rank;
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return chan * priv->ranksperchan + rank;
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}
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static void i5100_handle_ce(struct mem_ctl_info *mci,
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int ctlr,
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int chan,
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unsigned bank,
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unsigned rank,
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unsigned long syndrome,
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@ -407,12 +407,12 @@ static void i5100_handle_ce(struct mem_ctl_info *mci,
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unsigned ras,
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const char *msg)
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{
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const int csrow = i5100_rank_to_csrow(mci, ctlr, rank);
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const int csrow = i5100_rank_to_csrow(mci, chan, rank);
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printk(KERN_ERR
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"CE ctlr %d, bank %u, rank %u, syndrome 0x%lx, "
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"CE chan %d, bank %u, rank %u, syndrome 0x%lx, "
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"cas %u, ras %u, csrow %u, label \"%s\": %s\n",
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ctlr, bank, rank, syndrome, cas, ras,
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chan, bank, rank, syndrome, cas, ras,
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csrow, mci->csrows[csrow].channels[0].label, msg);
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mci->ce_count++;
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@ -421,7 +421,7 @@ static void i5100_handle_ce(struct mem_ctl_info *mci,
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}
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static void i5100_handle_ue(struct mem_ctl_info *mci,
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int ctlr,
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int chan,
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unsigned bank,
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unsigned rank,
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unsigned long syndrome,
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@ -429,23 +429,23 @@ static void i5100_handle_ue(struct mem_ctl_info *mci,
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unsigned ras,
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const char *msg)
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{
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const int csrow = i5100_rank_to_csrow(mci, ctlr, rank);
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const int csrow = i5100_rank_to_csrow(mci, chan, rank);
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printk(KERN_ERR
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"UE ctlr %d, bank %u, rank %u, syndrome 0x%lx, "
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"UE chan %d, bank %u, rank %u, syndrome 0x%lx, "
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"cas %u, ras %u, csrow %u, label \"%s\": %s\n",
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ctlr, bank, rank, syndrome, cas, ras,
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chan, bank, rank, syndrome, cas, ras,
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csrow, mci->csrows[csrow].channels[0].label, msg);
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mci->ue_count++;
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mci->csrows[csrow].ue_count++;
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}
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static void i5100_read_log(struct mem_ctl_info *mci, int ctlr,
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static void i5100_read_log(struct mem_ctl_info *mci, int chan,
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u32 ferr, u32 nerr)
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{
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struct i5100_priv *priv = mci->pvt_info;
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struct pci_dev *pdev = (ctlr) ? priv->ch1mm : priv->ch0mm;
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struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
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u32 dw;
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u32 dw2;
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unsigned syndrome = 0;
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@ -484,7 +484,7 @@ static void i5100_read_log(struct mem_ctl_info *mci, int ctlr,
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else
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msg = i5100_err_msg(nerr);
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i5100_handle_ce(mci, ctlr, bank, rank, syndrome, cas, ras, msg);
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i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
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}
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if (i5100_validlog_nrecmemvalid(dw)) {
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@ -506,7 +506,7 @@ static void i5100_read_log(struct mem_ctl_info *mci, int ctlr,
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else
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msg = i5100_err_msg(nerr);
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i5100_handle_ue(mci, ctlr, bank, rank, syndrome, cas, ras, msg);
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i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
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}
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pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
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@ -557,19 +557,19 @@ static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci,
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int csrow)
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{
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struct i5100_priv *priv = mci->pvt_info;
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const unsigned ctlr_rank = i5100_csrow_to_rank(mci, csrow);
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const unsigned ctlr = i5100_csrow_to_cntlr(mci, csrow);
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const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
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const unsigned chan = i5100_csrow_to_chan(mci, csrow);
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unsigned addr_lines;
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/* dimm present? */
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if (!priv->mtr[ctlr][ctlr_rank].present)
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if (!priv->mtr[chan][chan_rank].present)
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return 0ULL;
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addr_lines =
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I5100_DIMM_ADDR_LINES +
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priv->mtr[ctlr][ctlr_rank].numcol +
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priv->mtr[ctlr][ctlr_rank].numrow +
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priv->mtr[ctlr][ctlr_rank].numbank;
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priv->mtr[chan][chan_rank].numcol +
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priv->mtr[chan][chan_rank].numrow +
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priv->mtr[chan][chan_rank].numbank;
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return (unsigned long)
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((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
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@ -581,11 +581,11 @@ static void __devinit i5100_init_mtr(struct mem_ctl_info *mci)
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struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
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int i;
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for (i = 0; i < I5100_MAX_CTLRS; i++) {
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for (i = 0; i < I5100_CHANNELS; i++) {
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int j;
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struct pci_dev *pdev = mms[i];
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for (j = 0; j < I5100_MAX_RANKS_PER_CTLR; j++) {
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for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
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const unsigned addr =
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(j < 4) ? I5100_MTR_0 + j * 2 :
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I5100_MTR_4 + (j - 4) * 2;
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@ -644,7 +644,7 @@ static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
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* fill dimm chip select map
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*
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* FIXME:
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* o only valid for 4 ranks per controller
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* o only valid for 4 ranks per channel
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* o not the only way to may chip selects to dimm slots
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* o investigate if there is some way to obtain this map from the bios
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*/
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@ -653,9 +653,9 @@ static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci)
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struct i5100_priv *priv = mci->pvt_info;
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int i;
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WARN_ON(priv->ranksperctlr != 4);
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WARN_ON(priv->ranksperchan != 4);
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for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CTLR; i++) {
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for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
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int j;
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for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
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@ -677,10 +677,10 @@ static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev,
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struct i5100_priv *priv = mci->pvt_info;
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int i;
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for (i = 0; i < I5100_MAX_CTLRS; i++) {
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for (i = 0; i < I5100_CHANNELS; i++) {
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int j;
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for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CTLR; j++) {
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for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
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u8 rank;
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if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
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@ -720,7 +720,7 @@ static void __devinit i5100_init_interleaving(struct pci_dev *pdev,
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pci_read_config_word(pdev, I5100_AMIR_1, &w);
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priv->amir[1] = w;
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for (i = 0; i < I5100_MAX_CTLRS; i++) {
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for (i = 0; i < I5100_CHANNELS; i++) {
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int j;
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for (j = 0; j < 5; j++) {
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@ -747,7 +747,7 @@ static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
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for (i = 0; i < mci->nr_csrows; i++) {
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const unsigned long npages = i5100_npages(mci, i);
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const unsigned cntlr = i5100_csrow_to_cntlr(mci, i);
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const unsigned chan = i5100_csrow_to_chan(mci, i);
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const unsigned rank = i5100_csrow_to_rank(mci, i);
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if (!npages)
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@ -765,7 +765,7 @@ static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
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mci->csrows[i].grain = 32;
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mci->csrows[i].csrow_idx = i;
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mci->csrows[i].dtype =
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(priv->mtr[cntlr][rank].width == 4) ? DEV_X4 : DEV_X8;
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(priv->mtr[chan][rank].width == 4) ? DEV_X4 : DEV_X8;
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mci->csrows[i].ue_count = 0;
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mci->csrows[i].ce_count = 0;
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mci->csrows[i].mtype = MEM_RDDR2;
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@ -777,7 +777,7 @@ static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
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mci->csrows[i].channels[0].csrow = mci->csrows + i;
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snprintf(mci->csrows[i].channels[0].label,
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sizeof(mci->csrows[i].channels[0].label),
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"DIMM%u", i5100_rank_to_slot(mci, cntlr, rank));
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"DIMM%u", i5100_rank_to_slot(mci, chan, rank));
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total_pages += npages;
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}
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@ -816,7 +816,7 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
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ranksperch = !!(dw & (1 << 8)) * 2 + 4;
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if (ranksperch != 4) {
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/* FIXME: get 6 ranks / controller to work - need hw... */
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/* FIXME: get 6 ranks / channel to work - need hw... */
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printk(KERN_INFO "i5100_edac: unsupported configuration.\n");
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ret = -ENODEV;
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goto bail_pdev;
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@ -864,7 +864,7 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
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mci->dev = &pdev->dev;
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priv = mci->pvt_info;
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priv->ranksperctlr = ranksperch;
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priv->ranksperchan = ranksperch;
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priv->mc = pdev;
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priv->ch0mm = ch0mm;
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priv->ch1mm = ch1mm;
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