mirror of
https://github.com/adulau/aha.git
synced 2024-12-29 04:06:22 +00:00
[MIPS] DBAu1xx0 code style cleanup
Fix several errors and warnings given by checkpatch.pl: - macros with complex values not enclosed in parentheses; - leading spaces instead of tabs; - printk() without KERN_* facility level; - using simple_strtol() where strict_strtol() could be used; - line over 80 characters. In addition to these changes, also do the following: - initialize variable instead of assigning value later where it makes sense; - insert spaces between operator and its operands, also remove excess spaces there; - remove unneeded numeric literal type casts; - remove needless parentheses; - remove space after the type cast's closing parenthesis; - insert missing space before closing brace in the array initializers; - replace spaces after the macro name with tabs in the #define directives; - remove excess tabs after the macro name in the #define directives; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first/last line; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Sergei Shtylyov
Ralf Baechle
parent
a9633279cf
commit
abd14cc00d
5 changed files with 92 additions and 93 deletions
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@ -1,8 +1,8 @@
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#
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# Copyright 2000 MontaVista Software Inc.
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# Author: MontaVista Software, Inc.
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# ppopov@mvista.com or source@mvista.com
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# Copyright 2000, 2008 MontaVista Software Inc.
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# Author: MontaVista Software, Inc. <source@mvista.com>
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#
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# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
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#
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# Makefile for the Alchemy Semiconductor Db1x00 board.
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lib-y := init.o board_setup.o irqmap.o
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@ -3,9 +3,8 @@
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* BRIEF MODULE DESCRIPTION
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* Alchemy Db1x00 board setup.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -37,49 +36,49 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
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void board_reset(void)
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{
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/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
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/* Hit BCSR.SW_RESET[RESET] */
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bcsr->swreset = 0x0000;
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}
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void __init board_setup(void)
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{
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u32 pin_func;
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u32 pin_func = 0;
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pin_func = 0;
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/* not valid for 1550 */
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#if defined(CONFIG_IRDA) && (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
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/* set IRFIRSEL instead of GPIO15 */
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pin_func = au_readl(SYS_PINFUNC) | (u32)((1<<8));
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/* Not valid for Au1550 */
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#if defined(CONFIG_IRDA) && \
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(defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
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/* Set IRFIRSEL instead of GPIO15 */
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pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
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au_writel(pin_func, SYS_PINFUNC);
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/* power off until the driver is in use */
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/* Power off until the driver is in use */
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bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK;
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bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF;
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bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF;
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au_sync();
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#endif
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bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */
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#ifdef CONFIG_MIPS_MIRAGE
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/* enable GPIO[31:0] inputs */
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/* Enable GPIO[31:0] inputs */
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au_writel(0, SYS_PININPUTEN);
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/* GPIO[20] is output, tristate the other input primary GPIO's */
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au_writel((u32)(~(1<<20)), SYS_TRIOUTCLR);
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/* GPIO[20] is output, tristate the other input primary GPIOs */
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au_writel(~(1 << 20), SYS_TRIOUTCLR);
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/* set GPIO[210:208] instead of SSI_0 */
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pin_func = au_readl(SYS_PINFUNC) | (u32)(1);
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/* Set GPIO[210:208] instead of SSI_0 */
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pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
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/* set GPIO[215:211] for LED's */
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pin_func |= (u32)((5<<2));
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/* Set GPIO[215:211] for LEDs */
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pin_func |= 5 << 2;
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/* set GPIO[214:213] for more LED's */
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pin_func |= (u32)((5<<12));
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/* Set GPIO[214:213] for more LEDs */
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pin_func |= 5 << 12;
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/* set GPIO[207:200] instead of PCMCIA/LCD */
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pin_func |= (u32)((3<<17));
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/* Set GPIO[207:200] instead of PCMCIA/LCD */
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pin_func |= SYS_PF_LCD | SYS_PF_PC;
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au_writel(pin_func, SYS_PINFUNC);
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/* Enable speaker amplifier. This should
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/*
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* Enable speaker amplifier. This should
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* be part of the audio driver.
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*/
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au_writel(au_readl(GPIO2_DIR) | 0x200, GPIO2_DIR);
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@ -89,21 +88,21 @@ void __init board_setup(void)
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au_sync();
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#ifdef CONFIG_MIPS_DB1000
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printk("AMD Alchemy Au1000/Db1000 Board\n");
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printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
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#endif
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#ifdef CONFIG_MIPS_DB1500
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printk("AMD Alchemy Au1500/Db1500 Board\n");
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printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
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#endif
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#ifdef CONFIG_MIPS_DB1100
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printk("AMD Alchemy Au1100/Db1100 Board\n");
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printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
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#endif
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#ifdef CONFIG_MIPS_BOSPORUS
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printk("AMD Alchemy Bosporus Board\n");
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printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
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#endif
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#ifdef CONFIG_MIPS_MIRAGE
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printk("AMD Alchemy Mirage Board\n");
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printk(KERN_INFO "AMD Alchemy Mirage Board\n");
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#endif
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#ifdef CONFIG_MIPS_DB1550
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printk("AMD Alchemy Au1550/Db1550 Board\n");
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printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
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#endif
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}
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@ -2,9 +2,8 @@
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* BRIEF MODULE DESCRIPTION
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* PB1000 board setup
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -49,8 +48,8 @@ void __init prom_init(void)
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unsigned long memsize;
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prom_argc = fw_arg0;
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prom_argv = (char **) fw_arg1;
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prom_envp = (char **) fw_arg2;
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prom_argv = (char **)fw_arg1;
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prom_envp = (char **)fw_arg2;
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prom_init_cmdline();
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@ -58,6 +57,6 @@ void __init prom_init(void)
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if (!memsize_str)
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memsize = 0x04000000;
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else
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memsize = simple_strtol(memsize_str, NULL, 0);
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memsize = strict_strtol(memsize_str, 0, NULL);
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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}
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@ -32,32 +32,32 @@
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#ifdef CONFIG_MIPS_DB1500
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char irq_tab_alchemy[][5] __initdata = {
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[12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */
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[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
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[12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT371 */
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[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
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};
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#endif
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#ifdef CONFIG_MIPS_BOSPORUS
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char irq_tab_alchemy[][5] __initdata = {
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[11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */
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[12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */
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[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
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[11] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 11 - miniPCI */
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[12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - SN1741 */
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[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
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};
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#endif
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#ifdef CONFIG_MIPS_MIRAGE
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char irq_tab_alchemy[][5] __initdata = {
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[11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */
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[12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */
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[13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */
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[11] = { -1, INTD, INTX, INTX, INTX }, /* IDSEL 11 - SMI VGX */
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[12] = { -1, INTX, INTX, INTC, INTX }, /* IDSEL 12 - PNX1300 */
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[13] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 13 - miniPCI */
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};
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#endif
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#ifdef CONFIG_MIPS_DB1550
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char irq_tab_alchemy[][5] __initdata = {
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[11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */
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[12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
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[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
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[11] = { -1, INTC, INTX, INTX, INTX }, /* IDSEL 11 - on-board HPT371 */
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[12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
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[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
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};
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#endif
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@ -1,9 +1,8 @@
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/*
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* AMD Alchemy DB1x00 Reference Boards
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* AMD Alchemy DBAu1x00 Reference Boards
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* ########################################################################
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@ -32,26 +31,26 @@
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#ifdef CONFIG_MIPS_DB1550
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define SMBUS_PSC_BASE PSC2_BASE_ADDR
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#define I2S_PSC_BASE PSC3_BASE_ADDR
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define SMBUS_PSC_BASE PSC2_BASE_ADDR
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#define I2S_PSC_BASE PSC3_BASE_ADDR
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#define BCSR_KSEG1_ADDR 0xAF000000
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#define NAND_PHYS_ADDR 0x20000000
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#define BCSR_KSEG1_ADDR 0xAF000000
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#define NAND_PHYS_ADDR 0x20000000
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#else
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#define BCSR_KSEG1_ADDR 0xAE000000
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#endif
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/*
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* Overlay data structure of the Db1x00 board registers.
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* Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
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* Overlay data structure of the DBAu1x00 board registers.
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* Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
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*/
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typedef volatile struct
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{
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@ -138,18 +137,19 @@ typedef volatile struct
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#define BCSR_SWRESET_RESET 0x0080
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/* PCMCIA Db1x00 specific defines */
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
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/* PCMCIA DBAu1x00 specific defines */
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
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/* VPP/VCC */
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#define SET_VCC_VPP(VCC, VPP, SLOT)\
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((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
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((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
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/* SD controller macros */
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/*
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* Detect card.
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* SD controller macros
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*/
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/* Detect card. */
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#define mmc_card_inserted(_n_, _res_) \
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do { \
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BCSR * const bcsr = (BCSR *)0xAE000000; \
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@ -176,10 +176,10 @@ typedef volatile struct
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unsigned long mmc_pwr, mmc_wp, board_specific; \
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if ((_n_)) { \
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mmc_pwr = BCSR_BOARD_SD1_PWR; \
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mmc_wp = BCSR_BOARD_SD1_WP; \
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mmc_wp = BCSR_BOARD_SD1_WP; \
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} else { \
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mmc_pwr = BCSR_BOARD_SD0_PWR; \
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mmc_wp = BCSR_BOARD_SD0_WP; \
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mmc_wp = BCSR_BOARD_SD0_WP; \
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} \
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board_specific = au_readl((unsigned long)(&bcsr->specific)); \
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if (!(board_specific & mmc_wp)) {/* low means card present */ \
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@ -190,17 +190,19 @@ typedef volatile struct
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} while (0)
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/* NAND defines */
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/* Timing values as described in databook, * ns value stripped of
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/*
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* NAND defines
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*
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* Timing values as described in databook, * ns value stripped of the
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* lower 2 bits.
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* These defines are here rather than an SOC1550 generic file because
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* These defines are here rather than an Au1550 generic file because
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* the parts chosen on another board may be different and may require
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* different timings.
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*/
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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/* Bitfield shift amounts */
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#define NAND_T_H_SHIFT 0
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#define NAND_T_SU_SHIFT 8
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#define NAND_T_WH_SHIFT 12
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#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
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#define NAND_CS 1
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#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
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#define NAND_CS 1
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/* should be done by yamon */
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#define NAND_STCFG 0x00400005 /* 8-bit NAND */
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#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
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#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
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/* Should be done by YAMON */
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#define NAND_STCFG 0x00400005 /* 8-bit NAND */
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#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
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#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
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#endif /* __ASM_DB1X00_H */
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