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tg3: Add shmem options.
This patch adds some options obtained through shared memory. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
57e6983cbd
commit
a9daf36746
3 changed files with 123 additions and 8 deletions
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@ -33,6 +33,7 @@
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/brcmphy.h>
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#include <linux/if_vlan.h>
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#include <linux/ip.h>
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#include <linux/tcp.h>
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@ -869,6 +870,51 @@ static int tg3_mdio_reset(struct mii_bus *bp)
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return 0;
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}
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static void tg3_mdio_config(struct tg3 *tp)
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{
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u32 val;
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if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
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PHY_INTERFACE_MODE_RGMII)
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return;
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val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
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MAC_PHYCFG1_RGMII_SND_STAT_EN);
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
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val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
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val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
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}
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tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
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val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
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if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
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val |= MAC_PHYCFG2_INBAND_ENABLE;
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tw32(MAC_PHYCFG2, val);
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val = tr32(MAC_EXT_RGMII_MODE);
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val &= ~(MAC_RGMII_MODE_RX_INT_B |
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MAC_RGMII_MODE_RX_QUALITY |
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MAC_RGMII_MODE_RX_ACTIVITY |
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MAC_RGMII_MODE_RX_ENG_DET |
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MAC_RGMII_MODE_TX_ENABLE |
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MAC_RGMII_MODE_TX_LOWPWR |
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MAC_RGMII_MODE_TX_RESET);
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
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val |= MAC_RGMII_MODE_RX_INT_B |
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MAC_RGMII_MODE_RX_QUALITY |
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MAC_RGMII_MODE_RX_ACTIVITY |
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MAC_RGMII_MODE_RX_ENG_DET;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
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val |= MAC_RGMII_MODE_TX_ENABLE |
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MAC_RGMII_MODE_TX_LOWPWR |
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MAC_RGMII_MODE_TX_RESET;
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}
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tw32(MAC_EXT_RGMII_MODE, val);
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}
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static void tg3_mdio_start(struct tg3 *tp)
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{
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if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
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@ -880,6 +926,9 @@ static void tg3_mdio_start(struct tg3 *tp)
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tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
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tw32_f(MAC_MI_MODE, tp->mi_mode);
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udelay(80);
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if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
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tg3_mdio_config(tp);
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}
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static void tg3_mdio_stop(struct tg3 *tp)
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@ -895,6 +944,7 @@ static int tg3_mdio_init(struct tg3 *tp)
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{
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int i;
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u32 reg;
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struct phy_device *phydev;
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struct mii_bus *mdio_bus = &tp->mdio_bus;
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tg3_mdio_start(tp);
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@ -928,13 +978,34 @@ static int tg3_mdio_init(struct tg3 *tp)
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tg3_bmcr_reset(tp);
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i = mdiobus_register(mdio_bus);
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if (!i)
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tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
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else
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if (i) {
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printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
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tp->dev->name, i);
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return i;
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}
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tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
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phydev = tp->mdio_bus.phy_map[PHY_ADDR];
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switch (phydev->phy_id) {
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case TG3_PHY_ID_BCM50610:
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phydev->interface = PHY_INTERFACE_MODE_RGMII;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
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phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
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phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
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phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
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break;
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case TG3_PHY_ID_BCMAC131:
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phydev->interface = PHY_INTERFACE_MODE_MII;
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break;
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}
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tg3_mdio_config(tp);
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return 0;
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}
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static void tg3_mdio_fini(struct tg3 *tp)
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@ -1238,8 +1309,8 @@ static int tg3_phy_init(struct tg3 *tp)
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phydev = tp->mdio_bus.phy_map[PHY_ADDR];
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/* Attach the MAC to the PHY. */
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phydev = phy_connect(tp->dev, phydev->dev.bus_id,
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tg3_adjust_link, 0, phydev->interface);
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phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
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phydev->dev_flags, phydev->interface);
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if (IS_ERR(phydev)) {
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printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
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return PTR_ERR(phydev);
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@ -11219,7 +11290,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
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if (val == NIC_SRAM_DATA_SIG_MAGIC) {
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u32 nic_cfg, led_cfg;
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u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
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u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
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int eeprom_phy_serdes = 0;
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
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@ -11233,6 +11304,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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(ver > 0) && (ver < 0x100))
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
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if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
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NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
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eeprom_phy_serdes = 1;
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@ -11357,6 +11431,13 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
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tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
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}
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if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
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tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
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if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
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tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
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if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
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tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
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}
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}
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@ -529,7 +529,23 @@
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#define MAC_SERDES_CFG 0x00000590
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#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
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#define MAC_SERDES_STAT 0x00000594
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/* 0x598 --> 0x5b0 unused */
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/* 0x598 --> 0x5a0 unused */
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#define MAC_PHYCFG1 0x000005a0
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#define MAC_PHYCFG1_RGMII_INT 0x00000001
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#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
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#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
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#define MAC_PHYCFG1_TXC_DRV 0x20000000
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#define MAC_PHYCFG2 0x000005a4
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#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
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#define MAC_EXT_RGMII_MODE 0x000005a8
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#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
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#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
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#define MAC_RGMII_MODE_TX_RESET 0x00000004
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#define MAC_RGMII_MODE_RX_INT_B 0x00000100
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#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
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#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
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#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
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/* 0x5ac --> 0x5b0 unused */
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#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
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#define SERDES_RX_SIG_DETECT 0x00000400
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#define SG_DIG_CTRL 0x000005b0
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@ -1715,6 +1731,12 @@
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#define NIC_SRAM_DATA_CFG_3 0x00000d3c
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#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
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#define NIC_SRAM_DATA_CFG_4 0x00000d60
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#define NIC_SRAM_GMII_MODE 0x00000002
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#define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
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#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
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#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
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@ -2486,6 +2508,9 @@ struct tg3 {
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#define TG3_FLG3_MDIOBUS_INITED 0x00000020
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#define TG3_FLG3_MDIOBUS_PAUSED 0x00000040
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#define TG3_FLG3_PHY_CONNECTED 0x00000080
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#define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
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#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
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#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
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struct timer_list timer;
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u16 timer_counter;
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@ -2556,6 +2581,9 @@ struct tg3 {
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#define PHY_REV_BCM5401_B2 0x3
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#define PHY_REV_BCM5401_C0 0x6
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#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
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#define TG3_PHY_ID_BCM50610 0x143bd60
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#define TG3_PHY_ID_BCMAC131 0x143bc70
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u32 led_ctrl;
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u32 phy_otp;
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6
include/linux/brcmphy.h
Normal file
6
include/linux/brcmphy.h
Normal file
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@ -0,0 +1,6 @@
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#define PHY_BRCM_WIRESPEED_ENABLE 0x00000001
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#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000002
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#define PHY_BRCM_APD_CLK125_ENABLE 0x00000004
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#define PHY_BRCM_STD_IBND_DISABLE 0x00000008
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#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00000010
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#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00000020
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