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https://github.com/adulau/aha.git
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[ALSA] cmipci: update register definitions
Update comments for many register symbols, add some new register symbols, and rename a few ones. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
Clemens Ladisch
Jaroslav Kysela
parent
6935e68877
commit
a839a33d85
1 changed files with 109 additions and 64 deletions
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@ -95,30 +95,34 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
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#define CM_REG_FUNCTRL1 0x04
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#define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
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#define CM_ASFC_SHIFT 13
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#define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
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#define CM_DSFC_SHIFT 10
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#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
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#define CM_DSFC_SHIFT 13
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#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
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#define CM_ASFC_SHIFT 10
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#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
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#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
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#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
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#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
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#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
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#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
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#define CM_BREQ 0x00000010 /* bus master enabled */
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#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
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#define CM_UART_EN 0x00000004 /* UART */
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#define CM_JYSTK_EN 0x00000002 /* joy stick */
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#define CM_UART_EN 0x00000004 /* legacy UART */
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#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
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#define CM_ZVPORT 0x00000001 /* ZVPORT */
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#define CM_REG_CHFORMAT 0x08
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#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
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#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
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#define CM_CHB3D 0x20000000 /* 4 channels */
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#define CM_CHIP_MASK1 0x1f000000
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#define CM_CHIP_037 0x01000000
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#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
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#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
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#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
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#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
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#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
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#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
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#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
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/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
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@ -128,12 +132,18 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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#define CM_ADCBITLEN_14 0x00008000
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#define CM_ADCBITLEN_13 0x0000C000
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#define CM_ADCDACLEN_MASK 0x00003000
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#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
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#define CM_ADCDACLEN_060 0x00000000
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#define CM_ADCDACLEN_066 0x00001000
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#define CM_ADCDACLEN_130 0x00002000
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#define CM_ADCDACLEN_280 0x00003000
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#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
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#define CM_ADCDLEN_ORIGINAL 0x00000000
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#define CM_ADCDLEN_EXTRA 0x00001000
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#define CM_ADCDLEN_24K 0x00002000
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#define CM_ADCDLEN_WEIGHT 0x00003000
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#define CM_CH1_SRATE_176K 0x00000800
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#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
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#define CM_CH1_SRATE_88K 0x00000400
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@ -142,24 +152,25 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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#define CM_CH0_SRATE_88K 0x00000100
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#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
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#define CM_DBLSPDS 0x00000040
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#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
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#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
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#define CM_SPDLOCKED 0x00000010
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#define CM_CH1FMT_MASK 0x0000000C
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#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
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#define CM_CH1FMT_SHIFT 2
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#define CM_CH0FMT_MASK 0x00000003
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#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
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#define CM_CH0FMT_SHIFT 0
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#define CM_REG_INT_HLDCLR 0x0C
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#define CM_CHIP_MASK2 0xff000000
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#define CM_CHIP_8768 0x20000000
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#define CM_CHIP_055 0x08000000
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#define CM_CHIP_039 0x04000000
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#define CM_CHIP_039_6CH 0x01000000
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#define CM_CHIP_055 0x08000000
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#define CM_CHIP_8768 0x20000000
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#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
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#define CM_TDMA_INT_EN 0x00040000
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#define CM_CH1_INT_EN 0x00020000
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#define CM_CH0_INT_EN 0x00010000
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#define CM_INT_HOLD 0x00000002
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#define CM_INT_CLEAR 0x00000001
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#define CM_REG_INT_STATUS 0x10
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#define CM_INTR 0x80000000
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@ -178,12 +189,13 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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#define CM_CHINT0 0x00000001
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#define CM_REG_LEGACY_CTRL 0x14
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#define CM_NXCHG 0x80000000 /* h/w multi channels? */
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#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
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#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
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#define CM_VMPU_330 0x00000000
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#define CM_VMPU_320 0x20000000
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#define CM_VMPU_310 0x40000000
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#define CM_VMPU_300 0x60000000
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#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
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#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
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#define CM_VSBSEL_220 0x00000000
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#define CM_VSBSEL_240 0x04000000
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@ -194,44 +206,74 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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#define CM_FMSEL_3C8 0x01000000
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#define CM_FMSEL_3E0 0x02000000
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#define CM_FMSEL_3E8 0x03000000
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#define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
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#define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
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#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
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#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
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#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
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#define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
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#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
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#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
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#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
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#define CM_C_EECS 0x00040000
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#define CM_C_EEDI46 0x00020000
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#define CM_C_EECK46 0x00010000
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#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
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#define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
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#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
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#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
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#define CM_EXBASEN 0x00001000 /* external bass input enable */
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#define CM_REG_MISC_CTRL 0x18
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#define CM_PWD 0x80000000
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#define CM_PWD 0x80000000 /* power down */
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#define CM_RESET 0x40000000
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#define CM_SFIL_MASK 0x30000000
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#define CM_TXVX 0x08000000
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#define CM_N4SPK3D 0x04000000 /* 4ch output */
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#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
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#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
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#define CM_TXVX 0x08000000 /* model 037? */
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#define CM_N4SPK3D 0x04000000 /* copy front to rear */
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#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
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#define CM_SPDIF48K 0x01000000 /* write */
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#define CM_SPATUS48K 0x01000000 /* read */
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#define CM_ENDBDAC 0x00800000 /* enable dual dac */
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#define CM_ENDBDAC 0x00800000 /* enable double dac */
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#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
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#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
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#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
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#define CM_FM_EN 0x00080000 /* enalbe FM */
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#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
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#define CM_FM_EN 0x00080000 /* enable legacy FM */
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#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
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#define CM_VIDWPDSB 0x00010000
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#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
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#define CM_VIDWPDSB 0x00010000 /* model 037? */
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#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
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#define CM_MASK_EN 0x00004000
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#define CM_VIDWPPRT 0x00002000
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#define CM_SFILENB 0x00001000
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#define CM_MMODE_MASK 0x00000E00
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#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
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#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
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#define CM_VIDWPPRT 0x00002000 /* model 037? */
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#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
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#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
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#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
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#define CM_ENCENTER 0x00000080
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#define CM_FLINKON 0x00000040
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#define CM_FLINKOFF 0x00000020
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#define CM_MIDSMP 0x00000010
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#define CM_UPDDMA_MASK 0x0000000C
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#define CM_TWAIT_MASK 0x00000003
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#define CM_FLINKON 0x00000080 /* force modem link detection on, model 037 */
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#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
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#define CM_FLINKOFF 0x00000040 /* force modem link detection off, model 037 */
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#define CM_UNKNOWN_18_5 0x00000020 /* ? */
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#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
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#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
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#define CM_UPDDMA_2048 0x00000000
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#define CM_UPDDMA_1024 0x00000004
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#define CM_UPDDMA_512 0x00000008
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#define CM_UPDDMA_256 0x0000000C
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#define CM_TWAIT_MASK 0x00000003 /* model 037 */
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#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
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#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
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#define CM_REG_TDMA_POSITION 0x1C
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#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
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#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
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/* byte */
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#define CM_REG_MIXER0 0x20
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#define CM_REG_SBVR 0x20 /* write: sb16 version */
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#define CM_REG_DEV 0x20 /* read: hardware device version */
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#define CM_REG_MIXER21 0x21
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#define CM_UNKNOWN_21_MASK 0x78 /* ? */
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#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
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#define CM_PROINV 0x02 /* SBPro left/right channel switching */
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#define CM_X_SB16 0x01 /* SB16 compatible */
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#define CM_REG_SB16_DATA 0x22
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#define CM_REG_SB16_ADDR 0x23
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@ -246,8 +288,8 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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#define CM_FMMUTE_SHIFT 7
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#define CM_WSMUTE 0x40 /* mute PCM */
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#define CM_WSMUTE_SHIFT 6
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#define CM_SPK4 0x20 /* lin-in -> rear line out */
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#define CM_SPK4_SHIFT 5
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#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
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#define CM_REAR2LIN_SHIFT 5
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#define CM_REAR2FRONT 0x10 /* exchange rear/front */
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#define CM_REAR2FRONT_SHIFT 4
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#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
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@ -279,12 +321,13 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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#define CM_VAUXR_MASK 0x0f
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#define CM_REG_MISC 0x27
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#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
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#define CM_XGPO1 0x20
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// #define CM_XGPBIO 0x04
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#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
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#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
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#define CM_SPDVALID 0x02 /* spdif input valid check */
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#define CM_DMAUTO 0x01
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#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
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#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
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/*
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@ -325,18 +368,20 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
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/*
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* extended registers
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*/
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#define CM_REG_CH0_FRAME1 0x80 /* base address */
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#define CM_REG_CH0_FRAME2 0x84
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#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
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#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
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#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
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#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
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#define CM_REG_EXT_MISC 0x90
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#define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
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#define CM_CHB3D8C 0x20 /* 7.1 channels support */
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#define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
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#define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
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#define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
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#define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
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#define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
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#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
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#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
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#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
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#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
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#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
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#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
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#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
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#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
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/*
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* size of i/o region
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@ -717,9 +762,9 @@ static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int chann
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}
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if (cm->chip_version == 68) {
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if (channels == 8) {
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snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
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snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
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} else {
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snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
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snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
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}
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}
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spin_unlock_irq(&cm->reg_lock);
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@ -797,11 +842,11 @@ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
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freq = snd_cmipci_rate_freq(runtime->rate);
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val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
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if (rec->ch) {
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val &= ~CM_ASFC_MASK;
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val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
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} else {
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val &= ~CM_DSFC_MASK;
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val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
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} else {
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val &= ~CM_ASFC_MASK;
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val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
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}
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snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
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//snd_printd("cmipci: functrl1 = %08x\n", val);
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@ -2284,8 +2329,8 @@ DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* rever
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DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
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#endif
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DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
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// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
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// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
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// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
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// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
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// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
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DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
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@ -2355,11 +2400,11 @@ static inline unsigned int get_line_in_mode(struct cmipci *cm)
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unsigned int val;
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if (cm->chip_version >= 39) {
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val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
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if (val & CM_LINE_AS_BASS)
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if (val & (CM_CENTR2LIN | CM_BASE2LIN))
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return 2;
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}
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val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
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if (val & CM_SPK4)
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if (val & CM_REAR2LIN)
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return 1;
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return 0;
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||||
}
|
||||
|
|
@ -2383,13 +2428,13 @@ static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
|
|||
|
||||
spin_lock_irq(&cm->reg_lock);
|
||||
if (ucontrol->value.enumerated.item[0] == 2)
|
||||
change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
|
||||
change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
|
||||
else
|
||||
change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
|
||||
change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
|
||||
if (ucontrol->value.enumerated.item[0] == 1)
|
||||
change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
|
||||
change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
|
||||
else
|
||||
change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
|
||||
change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
|
||||
spin_unlock_irq(&cm->reg_lock);
|
||||
return change;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue