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sh: Fix up single page flushing to use PAGE_SIZE.

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Presently The SH-4 cache flushing code uses flush_cache_4096() for most
of the real flushing work, which breaks down to a fixed 4096 unroll and
increment. Not only is this sub-optimal for larger page sizes, it's also
uncovered a bug in sh4_flush_dcache_page() when large page sizes are used
and we have no cache aliases -- resulting in only a part of the page's
D-cache lines being written back.

Signed-off-by: Valentin Sitdikov <valentin.sitdikov@siemens.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Valentin Sitdikov 2009-10-16 14:15:38 +09:00 committed by Paul Mundt
parent 012abeea66
commit a7a7c0e1d1
1 changed files with 10 additions and 12 deletions
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22
arch/sh/mm/cache-sh4.c
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@ -26,7 +26,7 @@
#define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */ #define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */
#define MAX_ICACHE_PAGES 32 #define MAX_ICACHE_PAGES 32
static void __flush_cache_4096(unsigned long addr, unsigned long phys, static void __flush_cache_one(unsigned long addr, unsigned long phys,
unsigned long exec_offset); unsigned long exec_offset);
/* /*
@ -89,8 +89,7 @@ static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
local_irq_restore(flags); local_irq_restore(flags);
} }
static inline void flush_cache_4096(unsigned long start, static inline void flush_cache_one(unsigned long start, unsigned long phys)
unsigned long phys)
{ {
unsigned long flags, exec_offset = 0; unsigned long flags, exec_offset = 0;
@ -103,8 +102,7 @@ static inline void flush_cache_4096(unsigned long start,
exec_offset = 0x20000000; exec_offset = 0x20000000;
local_irq_save(flags); local_irq_save(flags);
__flush_cache_4096(start | SH_CACHE_ASSOC, __flush_cache_one(start | SH_CACHE_ASSOC, P1SEGADDR(phys), exec_offset);
P1SEGADDR(phys), exec_offset);
local_irq_restore(flags); local_irq_restore(flags);
} }
@ -129,8 +127,8 @@ static void sh4_flush_dcache_page(void *arg)
/* Loop all the D-cache */ /* Loop all the D-cache */
n = boot_cpu_data.dcache.n_aliases; n = boot_cpu_data.dcache.n_aliases;
for (i = 0; i < n; i++, addr += 4096) for (i = 0; i < n; i++, addr += PAGE_SIZE)
flush_cache_4096(addr, phys); flush_cache_one(addr, phys);
} }
wmb(); wmb();
@ -318,11 +316,11 @@ static void sh4_flush_cache_page(void *args)
/* We only need to flush D-cache when we have alias */ /* We only need to flush D-cache when we have alias */
if ((address^phys) & alias_mask) { if ((address^phys) & alias_mask) {
/* Loop 4K of the D-cache */ /* Loop 4K of the D-cache */
flush_cache_4096( flush_cache_one(
CACHE_OC_ADDRESS_ARRAY | (address & alias_mask), CACHE_OC_ADDRESS_ARRAY | (address & alias_mask),
phys); phys);
/* Loop another 4K of the D-cache */ /* Loop another 4K of the D-cache */
flush_cache_4096( flush_cache_one(
CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask), CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask),
phys); phys);
} }
@ -337,7 +335,7 @@ static void sh4_flush_cache_page(void *args)
* kernel has never executed the code through its identity * kernel has never executed the code through its identity
* translation. * translation.
*/ */
flush_cache_4096( flush_cache_one(
CACHE_IC_ADDRESS_ARRAY | (address & alias_mask), CACHE_IC_ADDRESS_ARRAY | (address & alias_mask),
phys); phys);
} }
@ -393,7 +391,7 @@ static void sh4_flush_cache_range(void *args)
} }
/** /**
* __flush_cache_4096 * __flush_cache_one
* *
* @addr: address in memory mapped cache array * @addr: address in memory mapped cache array
* @phys: P1 address to flush (has to match tags if addr has 'A' bit * @phys: P1 address to flush (has to match tags if addr has 'A' bit
@ -406,7 +404,7 @@ static void sh4_flush_cache_range(void *args)
* operation (purge/write-back) is selected by the lower 2 bits of * operation (purge/write-back) is selected by the lower 2 bits of
* 'phys'. * 'phys'.
*/ */
static void __flush_cache_4096(unsigned long addr, unsigned long phys, static void __flush_cache_one(unsigned long addr, unsigned long phys,
unsigned long exec_offset) unsigned long exec_offset)
{ {
int way_count; int way_count;