adulau/aha
1
0
Fork 0
mirror of https://github.com/adulau/aha.git synced 2024-12-27 03:06:10 +00:00
Code Issues Projects Releases Packages Wiki Activity

fix typo 'the same the\>'

Browse source 
Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
This commit is contained in:
Uwe Kleine-König 2008-02-03 14:59:11 +02:00 committed by Adrian Bunk
parent b885b27ce6
commit a247b5d594
3 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Documentation/arm/Sharp-LH/IOBarrier
View file

@ -32,7 +32,7 @@ BARRIER IO before the access to the SMC chip because the AEN latch
only needs occurs after the SMC IO write cycle. The routines that
implement this work-around make an additional concession which is to
disable interrupts during the IO sequence. Other hardware devices
(the LogicPD CPLD) have registers in the same the physical memory
(the LogicPD CPLD) have registers in the same physical memory
region as the SMC chip. An interrupt might allow an access to one of
those registers while SMC IO is being performed.

2
drivers/mtd/devices/doc2000.c
View file

@ -376,7 +376,7 @@ static int DoC_IdentChip(struct DiskOnChip *doc, int floor, int chip)
* hardware restriction. */
if (doc->mfr) {
if (doc->mfr == mfr && doc->id == id)
return 1; /* This is another the same the first */
return 1; /* This is the same as the first */
else
printk(KERN_WARNING
"Flash chip at floor %d, chip %d is different:\n",

4
include/asm-arm/arch-versatile/irqs.h
View file

@ -22,7 +22,7 @@
#include <asm/arch/platform.h>
/*
* IRQ interrupts definitions are the same the INT definitions
* IRQ interrupts definitions are the same as the INT definitions
* held within platform.h
*/
#define IRQ_VIC_START 0
@ -94,7 +94,7 @@
#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31
/*
* FIQ interrupts definitions are the same the INT definitions.
* FIQ interrupts definitions are the same as the INT definitions.
*/
#define FIQ_WDOGINT INT_WDOGINT
#define FIQ_SOFTINT INT_SOFTINT