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V4L/DVB (13089): cx25840: Separate set_audclk_freq functionality for the different chips
Separate out the set_audclk_freq() function into separate functions for the four families of cores. These cores all use slightly different sample clock schemes and may be assuming slightly (+/- 3 Hz) different reference frequencies. The code resuse was not worth the maintenance and testing headache of have all chips use the same function peppered with conditional logic. Added comments on how PLL and SRC parameters values are computed. Fixed a few bugs related to the shared code having a large number of conditional statements. Noted inconsistencies with FIXME in the comments. This is done in preparation for getting the CX2388[578] PLL/clock setting logic cleaned up for CX23888 analog video and IR (which need the VID PLL set right). Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Andy Walls
Mauro Carvalho Chehab
parent
2a03f03471
commit
9eef550a9a
1 changed files with 322 additions and 95 deletions
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@ -23,87 +23,137 @@
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#include "cx25840-core.h"
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static int set_audclk_freq(struct i2c_client *client, u32 freq)
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/*
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* Note: The PLL and SRC parameters are based on a reference frequency that
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* would ideally be:
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*
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* NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
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*
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* However, it's not the exact reference frequency that matters, only that the
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* firmware and modules that comprise the driver for a particular board all
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* use the same value (close to the ideal value).
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*
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* Comments below will note which reference frequency is assumed for various
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* parameters. They will usually be one of
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*
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* ref_freq = 28.636360 MHz
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* or
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* ref_freq = 28.636363 MHz
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*/
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static int cx25840_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (freq != 32000 && freq != 44100 && freq != 48000)
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return -EINVAL;
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/* common for all inputs and rates */
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x10 */
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if (!is_cx2388x(state) && !is_cx231xx(state))
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cx25840_write(client, 0x127, 0x50);
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if (state->aud_input != CX25840_AUDIO_SERIAL) {
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switch (freq) {
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case 32000:
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if (is_cx2388x(state)) {
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/* We don't have register values
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* so avoid destroying registers. */
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break;
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}
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10
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*/
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cx25840_write4(client, 0x108, 0x1006040f);
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if (!is_cx231xx(state)) {
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/* VID_PLL and AUX_PLL */
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cx25840_write4(client, 0x108, 0x1006040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/* AUX_PLL_FRAC */
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cx25840_write4(client, 0x110, 0x01bb39ee);
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}
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/*
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* AUX_PLL Fraction = 0x1bb39ee
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* 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384
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* 196.6 MHz pre-postdivide
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* FIXME < 200 MHz is out of specified valid range
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x01bb39ee);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src3/4/6_ctl = 0x0801f77f */
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/* src3/4/6_ctl */
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/* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
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cx25840_write4(client, 0x900, 0x0801f77f);
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cx25840_write4(client, 0x904, 0x0801f77f);
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cx25840_write4(client, 0x90c, 0x0801f77f);
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break;
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case 44100:
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if (is_cx2388x(state)) {
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/* We don't have register values
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* so avoid destroying registers. */
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break;
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}
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10
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*/
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cx25840_write4(client, 0x108, 0x1009040f);
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if (!is_cx231xx(state)) {
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/* VID_PLL and AUX_PLL */
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cx25840_write4(client, 0x108, 0x1009040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/* AUX_PLL_FRAC */
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cx25840_write4(client, 0x110, 0x00ec6bd6);
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}
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/*
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* AUX_PLL Fraction = 0x0ec6bd6
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* 28636363 * 0x9.7635eb0/0x10 = 44100 * 384
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* 271 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x00ec6bd6);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src3/4/6_ctl = 0x08016d59 */
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/* src3/4/6_ctl */
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/* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
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cx25840_write4(client, 0x900, 0x08016d59);
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cx25840_write4(client, 0x904, 0x08016d59);
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cx25840_write4(client, 0x90c, 0x08016d59);
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break;
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case 48000:
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if (is_cx2388x(state)) {
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/* We don't have register values
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* so avoid destroying registers. */
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break;
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}
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10
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*/
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cx25840_write4(client, 0x108, 0x100a040f);
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if (!is_cx231xx(state)) {
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/* VID_PLL and AUX_PLL */
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cx25840_write4(client, 0x108, 0x100a040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/* AUX_PLL_FRAC */
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cx25840_write4(client, 0x110, 0x0098d6e5);
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}
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/*
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* AUX_PLL Fraction = 0x098d6e5
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* 28636363 * 0xa.4c6b728/0x10 = 48000 * 384
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* 295 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x0098d6e5);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src3/4/6_ctl = 0x08014faa */
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/* src3/4/6_ctl */
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/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
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cx25840_write4(client, 0x900, 0x08014faa);
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cx25840_write4(client, 0x904, 0x08014faa);
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cx25840_write4(client, 0x90c, 0x08014faa);
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@ -112,91 +162,126 @@ static int set_audclk_freq(struct i2c_client *client, u32 freq)
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} else {
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switch (freq) {
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case 32000:
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if (is_cx2388x(state)) {
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/* We don't have register values
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* so avoid destroying registers. */
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break;
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}
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x08, AUX PLL Post Divider = 0x1e
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*/
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cx25840_write4(client, 0x108, 0x1e08040f);
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if (!is_cx231xx(state)) {
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/* VID_PLL and AUX_PLL */
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cx25840_write4(client, 0x108, 0x1e08040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/* AUX_PLL_FRAC */
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cx25840_write4(client, 0x110, 0x012a0869);
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}
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/*
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* AUX_PLL Fraction = 0x12a0869
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* 28636363 * 0x8.9504348/0x1e = 32000 * 256
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* 246 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x012a0869);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x14 = 256/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x54);
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if (is_cx2583x(state))
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break;
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/* src1_ctl = 0x08010000 */
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/* src1_ctl */
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/* 0x1.0000 = 32000/32000 */
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cx25840_write4(client, 0x8f8, 0x08010000);
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/* src3/4/6_ctl = 0x08020000 */
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/* src3/4/6_ctl */
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/* 0x2.0000 = 2 * (32000/32000) */
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cx25840_write4(client, 0x900, 0x08020000);
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cx25840_write4(client, 0x904, 0x08020000);
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cx25840_write4(client, 0x90c, 0x08020000);
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/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */
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cx25840_write(client, 0x127, 0x54);
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break;
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case 44100:
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if (is_cx2388x(state)) {
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/* We don't have register values
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* so avoid destroying registers. */
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break;
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}
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x18
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*/
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cx25840_write4(client, 0x108, 0x1809040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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if (!is_cx231xx(state)) {
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/* VID_PLL and AUX_PLL */
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cx25840_write4(client, 0x108, 0x1809040f);
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/*
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* AUX_PLL Fraction = 0x0ec6bd6
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* 28636363 * 0x9.7635eb0/0x18 = 44100 * 256
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* 271 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x00ec6bd6);
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/* AUX_PLL_FRAC */
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cx25840_write4(client, 0x110, 0x00ec6bd6);
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}
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src1_ctl = 0x08010000 */
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/* src1_ctl */
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/* 0x1.60cd = 44100/32000 */
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cx25840_write4(client, 0x8f8, 0x080160cd);
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/* src3/4/6_ctl = 0x08020000 */
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/* src3/4/6_ctl */
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/* 0x1.7385 = 2 * (32000/44100) */
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cx25840_write4(client, 0x900, 0x08017385);
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cx25840_write4(client, 0x904, 0x08017385);
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cx25840_write4(client, 0x90c, 0x08017385);
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break;
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case 48000:
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if (!is_cx2388x(state) && !is_cx231xx(state)) {
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/* VID_PLL and AUX_PLL */
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cx25840_write4(client, 0x108, 0x180a040f);
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x18
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*/
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cx25840_write4(client, 0x108, 0x180a040f);
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/* AUX_PLL_FRAC */
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cx25840_write4(client, 0x110, 0x0098d6e5);
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}
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/*
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* AUX_PLL Fraction = 0x098d6e5
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* 28636363 * 0xa.4c6b728/0x18 = 48000 * 256
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* 295 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x0098d6e5);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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if (!is_cx2388x(state) && !is_cx231xx(state)) {
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/* src1_ctl */
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cx25840_write4(client, 0x8f8, 0x08018000);
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/* src1_ctl */
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/* 0x1.8000 = 48000/32000 */
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cx25840_write4(client, 0x8f8, 0x08018000);
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/* src3/4/6_ctl */
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cx25840_write4(client, 0x900, 0x08015555);
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cx25840_write4(client, 0x904, 0x08015555);
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cx25840_write4(client, 0x90c, 0x08015555);
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} else {
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cx25840_write4(client, 0x8f8, 0x0801867c);
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cx25840_write4(client, 0x900, 0x08014faa);
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cx25840_write4(client, 0x904, 0x08014faa);
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cx25840_write4(client, 0x90c, 0x08014faa);
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}
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/* src3/4/6_ctl */
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/* 0x1.5555 = 2 * (32000/48000) */
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cx25840_write4(client, 0x900, 0x08015555);
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cx25840_write4(client, 0x904, 0x08015555);
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cx25840_write4(client, 0x90c, 0x08015555);
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break;
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}
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}
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@ -206,6 +291,148 @@ static int set_audclk_freq(struct i2c_client *client, u32 freq)
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return 0;
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}
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static inline int cx25836_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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return cx25840_set_audclk_freq(client, freq);
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}
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static int cx23885_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (state->aud_input != CX25840_AUDIO_SERIAL) {
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switch (freq) {
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case 32000:
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case 44100:
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case 48000:
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/* We don't have register values
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* so avoid destroying registers. */
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/* FIXME return -EINVAL; */
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break;
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}
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} else {
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switch (freq) {
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case 32000:
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case 44100:
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/* We don't have register values
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* so avoid destroying registers. */
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/* FIXME return -EINVAL; */
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break;
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case 48000:
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/* src1_ctl */
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/* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
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cx25840_write4(client, 0x8f8, 0x0801867c);
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/* src3/4/6_ctl */
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/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
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cx25840_write4(client, 0x900, 0x08014faa);
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cx25840_write4(client, 0x904, 0x08014faa);
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cx25840_write4(client, 0x90c, 0x08014faa);
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break;
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}
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}
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state->audclk_freq = freq;
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return 0;
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}
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static int cx231xx_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (state->aud_input != CX25840_AUDIO_SERIAL) {
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switch (freq) {
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case 32000:
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/* src3/4/6_ctl */
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/* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
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cx25840_write4(client, 0x900, 0x0801f77f);
|
||||
cx25840_write4(client, 0x904, 0x0801f77f);
|
||||
cx25840_write4(client, 0x90c, 0x0801f77f);
|
||||
break;
|
||||
|
||||
case 44100:
|
||||
/* src3/4/6_ctl */
|
||||
/* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
|
||||
cx25840_write4(client, 0x900, 0x08016d59);
|
||||
cx25840_write4(client, 0x904, 0x08016d59);
|
||||
cx25840_write4(client, 0x90c, 0x08016d59);
|
||||
break;
|
||||
|
||||
case 48000:
|
||||
/* src3/4/6_ctl */
|
||||
/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
|
||||
cx25840_write4(client, 0x900, 0x08014faa);
|
||||
cx25840_write4(client, 0x904, 0x08014faa);
|
||||
cx25840_write4(client, 0x90c, 0x08014faa);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (freq) {
|
||||
/* FIXME These cases make different assumptions about audclk */
|
||||
case 32000:
|
||||
/* src1_ctl */
|
||||
/* 0x1.0000 = 32000/32000 */
|
||||
cx25840_write4(client, 0x8f8, 0x08010000);
|
||||
|
||||
/* src3/4/6_ctl */
|
||||
/* 0x2.0000 = 2 * (32000/32000) */
|
||||
cx25840_write4(client, 0x900, 0x08020000);
|
||||
cx25840_write4(client, 0x904, 0x08020000);
|
||||
cx25840_write4(client, 0x90c, 0x08020000);
|
||||
break;
|
||||
|
||||
case 44100:
|
||||
/* src1_ctl */
|
||||
/* 0x1.60cd = 44100/32000 */
|
||||
cx25840_write4(client, 0x8f8, 0x080160cd);
|
||||
|
||||
/* src3/4/6_ctl */
|
||||
/* 0x1.7385 = 2 * (32000/44100) */
|
||||
cx25840_write4(client, 0x900, 0x08017385);
|
||||
cx25840_write4(client, 0x904, 0x08017385);
|
||||
cx25840_write4(client, 0x90c, 0x08017385);
|
||||
break;
|
||||
|
||||
case 48000:
|
||||
/* src1_ctl */
|
||||
/* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
|
||||
cx25840_write4(client, 0x8f8, 0x0801867c);
|
||||
|
||||
/* src3/4/6_ctl */
|
||||
/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
|
||||
cx25840_write4(client, 0x900, 0x08014faa);
|
||||
cx25840_write4(client, 0x904, 0x08014faa);
|
||||
cx25840_write4(client, 0x90c, 0x08014faa);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
state->audclk_freq = freq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int set_audclk_freq(struct i2c_client *client, u32 freq)
|
||||
{
|
||||
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
|
||||
|
||||
if (freq != 32000 && freq != 44100 && freq != 48000)
|
||||
return -EINVAL;
|
||||
|
||||
if (is_cx231xx(state))
|
||||
return cx231xx_set_audclk_freq(client, freq);
|
||||
|
||||
if (is_cx2388x(state))
|
||||
return cx23885_set_audclk_freq(client, freq);
|
||||
|
||||
if (is_cx2583x(state))
|
||||
return cx25836_set_audclk_freq(client, freq);
|
||||
|
||||
return cx25840_set_audclk_freq(client, freq);
|
||||
}
|
||||
|
||||
void cx25840_audio_set_path(struct i2c_client *client)
|
||||
{
|
||||
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
|
||||
|
|
|
|||
Loading…
Reference in a new issue