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iwlwifi: Add comments about CSR registers
Also regroup CSR_EEPROM and CSR_OTP bit field definitions. Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Ben Cahill
John W. Linville
parent
6ab10ff873
commit
9e595d24b1
1 changed files with 150 additions and 27 deletions
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@ -62,11 +62,29 @@
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*****************************************************************************/
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#ifndef __iwl_csr_h__
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#define __iwl_csr_h__
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/*=== CSR (control and status registers) ===*/
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/*
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* CSR (control and status registers)
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*
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* CSR registers are mapped directly into PCI bus space, and are accessible
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* whenever platform supplies power to device, even when device is in
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* low power states due to driver-invoked device resets
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* (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
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*
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* Use iwl_write32() and iwl_read32() family to access these registers;
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* these provide simple PCI bus access, without waking up the MAC.
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* Do not use iwl_write_direct32() family for these registers;
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* no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
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* The MAC (uCode processor, etc.) does not need to be powered up for accessing
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* the CSR registers.
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*
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* NOTE: Newer devices using one-time-programmable (OTP) memory
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* require device to be awake in order to read this memory
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* via CSR_EEPROM and CSR_OTP registers
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*/
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#define CSR_BASE (0x000)
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#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
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#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
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#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
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#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
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#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
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#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
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@ -74,42 +92,65 @@
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#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
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#define CSR_GP_CNTRL (CSR_BASE+0x024)
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/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
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#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
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/*
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* Hardware revision info
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* Bit fields:
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* 31-8: Reserved
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* 7-4: Type of device: 0x0 = 4965, 0xd = 3945
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* 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
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* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
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* 1-0: "Dash" value, as in A-1, etc.
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* 1-0: "Dash" (-) value, as in A-1, etc.
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*
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* NOTE: Revision step affects calculation of CCK txpower for 4965.
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* NOTE: See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
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*/
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#define CSR_HW_REV (CSR_BASE+0x028)
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/* EEPROM reads */
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/*
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* EEPROM and OTP (one-time-programmable) memory reads
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*
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* NOTE: For (newer) devices using OTP, device must be awake, initialized via
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* apm_ops.init() in order to read. Older devices (3945/4965/5000)
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* use EEPROM and do not require this.
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*/
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#define CSR_EEPROM_REG (CSR_BASE+0x02c)
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#define CSR_EEPROM_GP (CSR_BASE+0x030)
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#define CSR_OTP_GP_REG (CSR_BASE+0x034)
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#define CSR_GIO_REG (CSR_BASE+0x03C)
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#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
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#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
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/*
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* UCODE-DRIVER GP (general purpose) mailbox registers.
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* SET/CLR registers set/clear bit(s) if "1" is written.
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*/
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#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
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#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
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#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
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#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
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#define CSR_LED_REG (CSR_BASE+0x094)
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#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
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/* GIO Chicken Bits (PCI Express bus link power management) */
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#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
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#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
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/* Analog phase-lock-loop configuration */
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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/*
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* Indicates hardware rev, to determine CCK backoff for txpower calculation.
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* CSR Hardware Revision Workaround Register. Indicates hardware rev;
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* "step" determines CCK backoff for txpower calculation. Used for 4965 only.
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* See also CSR_HW_REV register.
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* Bit fields:
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* 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
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* 1-0: "Dash" (-) value, as in C-1, etc.
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*/
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#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
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#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
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#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
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@ -126,11 +167,11 @@
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#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
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#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
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#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
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#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000)
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000)
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#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000)
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#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
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#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
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#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
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#define CSR_INT_PERIODIC_DIS (0x00)
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#define CSR_INT_PERIODIC_ENA (0xFF)
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@ -198,7 +239,44 @@
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#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
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#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
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/* GP (general purpose) CONTROL */
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/*
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* GP (general purpose) CONTROL REGISTER
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* Bit fields:
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* 27: HW_RF_KILL_SW
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* Indicates state of (platform's) hardware RF-Kill switch
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* 26-24: POWER_SAVE_TYPE
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* Indicates current power-saving mode:
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* 000 -- No power saving
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* 001 -- MAC power-down
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* 010 -- PHY (radio) power-down
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* 011 -- Error
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* 9-6: SYS_CONFIG
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* Indicates current system configuration, reflecting pins on chip
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* as forced high/low by device circuit board.
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* 4: GOING_TO_SLEEP
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* Indicates MAC is entering a power-saving sleep power-down.
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* Not a good time to access device-internal resources.
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* 3: MAC_ACCESS_REQ
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* Host sets this to request and maintain MAC wakeup, to allow host
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* access to device-internal resources. Host must wait for
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* MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
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* device registers.
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* 2: INIT_DONE
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* Host sets this to put device into fully operational D0 power mode.
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* Host resets this after SW_RESET to put device into low power mode.
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* 0: MAC_CLOCK_READY
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* Indicates MAC (ucode processor, etc.) is powered up and can run.
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* Internal resources are accessible.
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* NOTE: This does not indicate that the processor is actually running.
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* NOTE: This does not indicate that 4965 or 3945 has completed
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* init or post-power-down restore of internal SRAM memory.
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* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
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* SRAM is restored and uCode is in normal operation mode.
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* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
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* do not need to save/restore it.
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* NOTE: After device reset, this bit remains "0" until host sets
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* INIT_DONE
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*/
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#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
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#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
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#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
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@ -231,28 +309,58 @@
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#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
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/* EEPROM GP */
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#define CSR_EEPROM_GP_VALID_MSK (0x00000007)
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#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
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#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
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#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
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#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
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#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
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#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
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/* One-time-programmable memory general purpose reg */
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#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
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#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
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#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
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#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
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/* GP REG */
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#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
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#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
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#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
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#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
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#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
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/* EEPROM signature */
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#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
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#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
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#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
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#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
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/* CSR GIO */
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#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
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/* UCODE DRV GP */
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/*
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* UCODE-DRIVER GP (general purpose) mailbox register 1
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* Host driver and uCode write and/or read this register to communicate with
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* each other.
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* Bit fields:
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* 4: UCODE_DISABLE
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* Host sets this to request permanent halt of uCode, same as
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* sending CARD_STATE command with "halt" bit set.
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* 3: CT_KILL_EXIT
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* Host sets this to request exit from CT_KILL state, i.e. host thinks
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* device temperature is low enough to continue normal operation.
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* 2: CMD_BLOCKED
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* Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
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* to release uCode to clear all Tx and command queues, enter
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* unassociated mode, and power down.
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* NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
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* 1: SW_BIT_RFKILL
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* Host sets this when issuing CARD_STATE command to request
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* device sleep.
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* 0: MAC_SLEEP
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* uCode sets this when preparing a power-saving power-down.
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* uCode resets this when power-up is complete and SRAM is sane.
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* NOTE: 3945/4965 saves internal SRAM data to host when powering down,
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* and must restore this data after powering back up.
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* MAC_SLEEP is the best indication that restore is complete.
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* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
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* do not need to save/restore it.
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*/
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#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
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#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
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#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
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@ -265,7 +373,7 @@
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#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
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/* GI Chicken Bits */
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/* GIO Chicken Bits (PCI Express bus link power management) */
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
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@ -285,8 +393,23 @@
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#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
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#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
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/*=== HBUS (Host-side Bus) ===*/
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/*
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* HBUS (Host-side Bus)
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*
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* HBUS registers are mapped directly into PCI bus space, but are used
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* to indirectly access device's internal memory or registers that
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* may be powered-down.
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*
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* Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
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* host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
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* to make sure the MAC (uCode processor, etc.) is powered up for accessing
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* internal resources.
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*
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* Do not use iwl_write32()/iwl_read32() family to access these registers;
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* these provide only simple PCI bus access, without waking up the MAC.
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*/
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#define HBUS_BASE (0x400)
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/*
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* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
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* structures, error log, event log, verifying uCode load).
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@ -301,6 +424,10 @@
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#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
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#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
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/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
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#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
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#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
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/*
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* Registers for accessing device's internal peripheral registers
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* (e.g. SCD, BSM, etc.). First write to address register,
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@ -315,16 +442,12 @@
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#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
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/*
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* Per-Tx-queue write pointer (index, really!) (3945 and 4965).
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* Per-Tx-queue write pointer (index, really!)
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* Indicates index to next TFD that driver will fill (1 past latest filled).
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* Bit usage:
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* 0-7: queue write index
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* 11-8: queue selector
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*/
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#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
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#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
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#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
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#endif /* !__iwl_csr_h__ */
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