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flush icache before set_pte() on ia64: flush icache at set_pte
Current ia64 kernel flushes icache by lazy_mmu_prot_update() *after* set_pte(). This is too late. This patch removes lazy_mmu_prot_update and add modfied set_pte() for flushing if necessary. This patch flush icache of a page when new pte has exec bit. && new pte has present bit && new pte is user's page. && (old *ptep is not present || new pte's pfn is not same to old *ptep's ptn) && new pte's page has no Pg_arch_1 bit. Pg_arch_1 is set when a page is cache consistent. I think this condition checks are much easier to understand than considering "Where sync_icache_dcache() should be inserted ?". pte_user() for ia64 was removed by http://lkml.org/lkml/2007/6/12/67 as clean-up. So, I added it again. Signed-off-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Christoph Lameter <clameter@sgi.com> Cc: Hugh Dickins <hugh@veritas.com> Cc: Nick Piggin <nickpiggin@yahoo.com.au> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
parent
97ee052461
commit
954ffcb35f
9 changed files with 33 additions and 39 deletions
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@ -133,12 +133,6 @@ changes occur:
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The ia64 sn2 platform is one example of a platform
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The ia64 sn2 platform is one example of a platform
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that uses this interface.
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that uses this interface.
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8) void lazy_mmu_prot_update(pte_t pte)
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This interface is called whenever the protection on
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any user PTEs change. This interface provides a notification
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to architecture specific code to take appropriate action.
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Next, we have the cache flushing interfaces. In general, when Linux
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Next, we have the cache flushing interfaces. In general, when Linux
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is changing an existing virtual-->physical mapping to a new value,
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is changing an existing virtual-->physical mapping to a new value,
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the sequence will be in one of the following forms:
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the sequence will be in one of the following forms:
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@ -54,15 +54,12 @@ struct page *zero_page_memmap_ptr; /* map entry for zero page */
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EXPORT_SYMBOL(zero_page_memmap_ptr);
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EXPORT_SYMBOL(zero_page_memmap_ptr);
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void
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void
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lazy_mmu_prot_update (pte_t pte)
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__ia64_sync_icache_dcache (pte_t pte)
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{
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{
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unsigned long addr;
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unsigned long addr;
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struct page *page;
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struct page *page;
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unsigned long order;
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unsigned long order;
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if (!pte_exec(pte))
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return; /* not an executable page... */
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page = pte_page(pte);
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page = pte_page(pte);
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addr = (unsigned long) page_address(page);
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addr = (unsigned long) page_address(page);
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@ -125,10 +125,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres
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#define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
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#define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
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#endif
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#endif
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#ifndef __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
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#define lazy_mmu_prot_update(pte) do { } while (0)
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#endif
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#ifndef __HAVE_ARCH_MOVE_PTE
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#ifndef __HAVE_ARCH_MOVE_PTE
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#define move_pte(pte, prot, old_addr, new_addr) (pte)
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#define move_pte(pte, prot, old_addr, new_addr) (pte)
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#endif
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#endif
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@ -223,12 +223,6 @@ ia64_phys_addr_valid (unsigned long addr)
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* page table.
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* page table.
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*/
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*/
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/*
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* On some architectures, special things need to be done when setting
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* the PTE in a page table. Nothing special needs to be on IA-64.
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*/
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#define set_pte(ptep, pteval) (*(ptep) = (pteval))
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
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#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
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#ifdef CONFIG_VIRTUAL_MEM_MAP
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#ifdef CONFIG_VIRTUAL_MEM_MAP
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@ -320,6 +314,36 @@ ia64_phys_addr_valid (unsigned long addr)
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#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
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#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
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#define pte_mkhuge(pte) (__pte(pte_val(pte)))
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#define pte_mkhuge(pte) (__pte(pte_val(pte)))
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/*
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* Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
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* sync icache and dcache when we insert *new* executable page.
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* __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache
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* if necessary.
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*
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* set_pte() is also called by the kernel, but we can expect that the kernel
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* flushes icache explicitly if necessary.
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*/
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#define pte_present_exec_user(pte)\
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((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
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(_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
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extern void __ia64_sync_icache_dcache(pte_t pteval);
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static inline void set_pte(pte_t *ptep, pte_t pteval)
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{
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/* page is present && page is user && page is executable
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* && (page swapin or new page or page migraton
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* || copy_on_write with page copying.)
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*/
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if (pte_present_exec_user(pteval) &&
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(!pte_present(*ptep) ||
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pte_pfn(*ptep) != pte_pfn(pteval)))
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/* load_module() calles flush_icache_range() explicitly*/
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__ia64_sync_icache_dcache(pteval);
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*ptep = pteval;
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}
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/*
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/*
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* Make page protection values cacheable, uncacheable, or write-
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* Make page protection values cacheable, uncacheable, or write-
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* combining. Note that "protection" is really a misnomer here as the
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* combining. Note that "protection" is really a misnomer here as the
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@ -489,12 +513,6 @@ extern struct page *zero_page_memmap_ptr;
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#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
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#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
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#endif
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#endif
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/*
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* IA-64 doesn't have any external MMU info: the page tables contain all the necessary
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* information. However, we use this routine to take care of any (delayed) i-cache
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* flushing that may be necessary.
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*/
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extern void lazy_mmu_prot_update (pte_t pte);
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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/*
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/*
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@ -584,7 +602,7 @@ extern void lazy_mmu_prot_update (pte_t pte);
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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#define __HAVE_ARCH_PTE_SAME
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#define __HAVE_ARCH_PTE_SAME
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#define __HAVE_ARCH_PGD_OFFSET_GATE
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#define __HAVE_ARCH_PGD_OFFSET_GATE
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#define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
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#ifndef CONFIG_PGTABLE_4
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#ifndef CONFIG_PGTABLE_4
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#include <asm-generic/pgtable-nopud.h>
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#include <asm-generic/pgtable-nopud.h>
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@ -355,7 +355,6 @@ static void set_huge_ptep_writable(struct vm_area_struct *vma,
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entry = pte_mkwrite(pte_mkdirty(*ptep));
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entry = pte_mkwrite(pte_mkdirty(*ptep));
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if (ptep_set_access_flags(vma, address, ptep, entry, 1)) {
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if (ptep_set_access_flags(vma, address, ptep, entry, 1)) {
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update_mmu_cache(vma, address, entry);
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update_mmu_cache(vma, address, entry);
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lazy_mmu_prot_update(entry);
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}
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}
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}
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}
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@ -708,7 +707,6 @@ void hugetlb_change_protection(struct vm_area_struct *vma,
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pte = huge_ptep_get_and_clear(mm, address, ptep);
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pte = huge_ptep_get_and_clear(mm, address, ptep);
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pte = pte_mkhuge(pte_modify(pte, newprot));
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pte = pte_mkhuge(pte_modify(pte, newprot));
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set_huge_pte_at(mm, address, ptep, pte);
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set_huge_pte_at(mm, address, ptep, pte);
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lazy_mmu_prot_update(pte);
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}
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}
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}
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}
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spin_unlock(&mm->page_table_lock);
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spin_unlock(&mm->page_table_lock);
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@ -1611,10 +1611,8 @@ static int do_wp_page(struct mm_struct *mm, struct vm_area_struct *vma,
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flush_cache_page(vma, address, pte_pfn(orig_pte));
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flush_cache_page(vma, address, pte_pfn(orig_pte));
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entry = pte_mkyoung(orig_pte);
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entry = pte_mkyoung(orig_pte);
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entry = maybe_mkwrite(pte_mkdirty(entry), vma);
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entry = maybe_mkwrite(pte_mkdirty(entry), vma);
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if (ptep_set_access_flags(vma, address, page_table, entry,1)) {
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if (ptep_set_access_flags(vma, address, page_table, entry,1))
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update_mmu_cache(vma, address, entry);
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update_mmu_cache(vma, address, entry);
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lazy_mmu_prot_update(entry);
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}
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ret |= VM_FAULT_WRITE;
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ret |= VM_FAULT_WRITE;
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goto unlock;
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goto unlock;
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}
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}
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@ -1650,7 +1648,6 @@ gotten:
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flush_cache_page(vma, address, pte_pfn(orig_pte));
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flush_cache_page(vma, address, pte_pfn(orig_pte));
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entry = mk_pte(new_page, vma->vm_page_prot);
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entry = mk_pte(new_page, vma->vm_page_prot);
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entry = maybe_mkwrite(pte_mkdirty(entry), vma);
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entry = maybe_mkwrite(pte_mkdirty(entry), vma);
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lazy_mmu_prot_update(entry);
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/*
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/*
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* Clear the pte entry and flush it first, before updating the
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* Clear the pte entry and flush it first, before updating the
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* pte with the new entry. This will avoid a race condition
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* pte with the new entry. This will avoid a race condition
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/* No need to invalidate - it was non-present before */
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/* No need to invalidate - it was non-present before */
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update_mmu_cache(vma, address, entry);
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update_mmu_cache(vma, address, entry);
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lazy_mmu_prot_update(entry);
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unlock:
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unlock:
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pte_unmap_unlock(page_table, ptl);
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pte_unmap_unlock(page_table, ptl);
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return 0;
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return 0;
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@ -2333,7 +2329,6 @@ static int __do_fault(struct mm_struct *mm, struct vm_area_struct *vma,
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/* no need to invalidate: a not-present page won't be cached */
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/* no need to invalidate: a not-present page won't be cached */
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update_mmu_cache(vma, address, entry);
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update_mmu_cache(vma, address, entry);
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lazy_mmu_prot_update(entry);
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} else {
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} else {
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if (anon)
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if (anon)
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page_cache_release(page);
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page_cache_release(page);
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@ -2505,7 +2500,6 @@ static inline int handle_pte_fault(struct mm_struct *mm,
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entry = pte_mkyoung(entry);
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entry = pte_mkyoung(entry);
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if (ptep_set_access_flags(vma, address, pte, entry, write_access)) {
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if (ptep_set_access_flags(vma, address, pte, entry, write_access)) {
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update_mmu_cache(vma, address, entry);
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update_mmu_cache(vma, address, entry);
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lazy_mmu_prot_update(entry);
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} else {
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} else {
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/*
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/*
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* This is needed only for protection faults but the arch code
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* This is needed only for protection faults but the arch code
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@ -181,7 +181,6 @@ static void remove_migration_pte(struct vm_area_struct *vma,
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/* No need to invalidate - it was non-present before */
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/* No need to invalidate - it was non-present before */
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update_mmu_cache(vma, addr, pte);
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update_mmu_cache(vma, addr, pte);
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lazy_mmu_prot_update(pte);
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out:
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out:
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pte_unmap_unlock(ptep, ptl);
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pte_unmap_unlock(ptep, ptl);
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@ -53,7 +53,6 @@ static void change_pte_range(struct mm_struct *mm, pmd_t *pmd,
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if (dirty_accountable && pte_dirty(ptent))
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if (dirty_accountable && pte_dirty(ptent))
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ptent = pte_mkwrite(ptent);
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ptent = pte_mkwrite(ptent);
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set_pte_at(mm, addr, pte, ptent);
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set_pte_at(mm, addr, pte, ptent);
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lazy_mmu_prot_update(ptent);
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#ifdef CONFIG_MIGRATION
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#ifdef CONFIG_MIGRATION
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} else if (!pte_file(oldpte)) {
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} else if (!pte_file(oldpte)) {
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swp_entry_t entry = pte_to_swp_entry(oldpte);
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swp_entry_t entry = pte_to_swp_entry(oldpte);
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entry = pte_wrprotect(entry);
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entry = pte_wrprotect(entry);
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entry = pte_mkclean(entry);
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entry = pte_mkclean(entry);
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set_pte_at(mm, address, pte, entry);
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set_pte_at(mm, address, pte, entry);
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lazy_mmu_prot_update(entry);
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ret = 1;
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ret = 1;
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}
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}
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