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ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size

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Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.

List of CPUs with cache line size != 32 should be expanded later.

Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Kirill A. Shutemov 2009-09-15 10:23:53 +01:00 committed by Russell King
parent 59fcf48fde
commit 910a17e57a
2 changed files with 6 additions and 1 deletions
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2
arch/arm/include/asm/cache.h
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@ -4,7 +4,7 @@
#ifndef __ASMARM_CACHE_H
#define __ASMARM_CACHE_H
#define L1_CACHE_SHIFT 5
#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*

5
arch/arm/mm/Kconfig
View file

@ -771,3 +771,8 @@ config CACHE_XSC3L2
select OUTER_CACHE
help
This option enables the L2 cache on XScale3.
config ARM_L1_CACHE_SHIFT
int
default 6 if ARCH_OMAP3
default 5