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gpio: add Intel Moorestown Platform Langwell chip gpio driver
The Langwell chip is the IO hub for Intel Moorestown platform which has a 64-pin gpio block device inside. It is exposed as a dedicated PCI device. We use it to control outside peripheral as well as to do IRQ demuxing. The gpio block uses MSI to send level type interrupt to IOAPIC. Signed-off-by: Alek Du <alek.du@intel.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Alek Du
Linus Torvalds
parent
4cf8e53b3b
commit
8bf0261770
3 changed files with 304 additions and 0 deletions
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@ -180,6 +180,12 @@ config GPIO_BT8XX
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If unsure, say N.
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config GPIO_LANGWELL
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bool "Intel Moorestown Platform Langwell GPIO support"
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depends on PCI
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help
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Say Y here to support Intel Moorestown platform GPIO.
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comment "SPI GPIO expanders:"
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config GPIO_MAX7301
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@ -4,6 +4,7 @@ ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG
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obj-$(CONFIG_GPIOLIB) += gpiolib.o
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obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o
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obj-$(CONFIG_GPIO_MAX7301) += max7301.o
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obj-$(CONFIG_GPIO_MAX732X) += max732x.o
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obj-$(CONFIG_GPIO_MC33880) += mc33880.o
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297
drivers/gpio/langwell_gpio.c
Normal file
297
drivers/gpio/langwell_gpio.c
Normal file
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@ -0,0 +1,297 @@
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/* langwell_gpio.c Moorestown platform Langwell chip GPIO driver
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* Copyright (c) 2008 - 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Supports:
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* Moorestown platform Langwell chip.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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struct lnw_gpio_register {
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u32 GPLR[2];
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u32 GPDR[2];
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u32 GPSR[2];
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u32 GPCR[2];
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u32 GRER[2];
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u32 GFER[2];
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u32 GEDR[2];
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};
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struct lnw_gpio {
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struct gpio_chip chip;
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struct lnw_gpio_register *reg_base;
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spinlock_t lock;
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unsigned irq_base;
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};
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static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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u8 reg = offset / 32;
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void __iomem *gplr;
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gplr = (void __iomem *)(&lnw->reg_base->GPLR[reg]);
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return readl(gplr) & BIT(offset % 32);
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}
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static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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u8 reg = offset / 32;
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void __iomem *gpsr, *gpcr;
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if (value) {
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gpsr = (void __iomem *)(&lnw->reg_base->GPSR[reg]);
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writel(BIT(offset % 32), gpsr);
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} else {
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gpcr = (void __iomem *)(&lnw->reg_base->GPCR[reg]);
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writel(BIT(offset % 32), gpcr);
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}
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}
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static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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u8 reg = offset / 32;
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u32 value;
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unsigned long flags;
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void __iomem *gpdr;
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gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
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spin_lock_irqsave(&lnw->lock, flags);
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value = readl(gpdr);
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value &= ~BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&lnw->lock, flags);
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return 0;
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}
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static int lnw_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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u8 reg = offset / 32;
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unsigned long flags;
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void __iomem *gpdr;
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lnw_gpio_set(chip, offset, value);
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gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
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spin_lock_irqsave(&lnw->lock, flags);
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value = readl(gpdr);
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value |= BIT(offset % 32);;
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writel(value, gpdr);
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spin_unlock_irqrestore(&lnw->lock, flags);
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return 0;
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}
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static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
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return lnw->irq_base + offset;
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}
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static int lnw_irq_type(unsigned irq, unsigned type)
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{
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struct lnw_gpio *lnw = get_irq_chip_data(irq);
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u32 gpio = irq - lnw->irq_base;
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u8 reg = gpio / 32;
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unsigned long flags;
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u32 value;
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void __iomem *grer = (void __iomem *)(&lnw->reg_base->GRER[reg]);
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void __iomem *gfer = (void __iomem *)(&lnw->reg_base->GFER[reg]);
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if (gpio < 0 || gpio > lnw->chip.ngpio)
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return -EINVAL;
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spin_lock_irqsave(&lnw->lock, flags);
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if (type & IRQ_TYPE_EDGE_RISING)
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value = readl(grer) | BIT(gpio % 32);
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else
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value = readl(grer) & (~BIT(gpio % 32));
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writel(value, grer);
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if (type & IRQ_TYPE_EDGE_FALLING)
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value = readl(gfer) | BIT(gpio % 32);
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else
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value = readl(gfer) & (~BIT(gpio % 32));
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writel(value, gfer);
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spin_unlock_irqrestore(&lnw->lock, flags);
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return 0;
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};
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static void lnw_irq_unmask(unsigned irq)
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{
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struct lnw_gpio *lnw = get_irq_chip_data(irq);
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u32 gpio = irq - lnw->irq_base;
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u8 reg = gpio / 32;
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void __iomem *gedr;
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gedr = (void __iomem *)(&lnw->reg_base->GEDR[reg]);
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writel(BIT(gpio % 32), gedr);
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};
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static void lnw_irq_mask(unsigned irq)
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{
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};
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static struct irq_chip lnw_irqchip = {
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.name = "LNW-GPIO",
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.mask = lnw_irq_mask,
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.unmask = lnw_irq_unmask,
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.set_type = lnw_irq_type,
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};
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static struct pci_device_id lnw_gpio_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
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static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct lnw_gpio *lnw = (struct lnw_gpio *)get_irq_data(irq);
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u32 reg, gpio;
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void __iomem *gedr;
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u32 gedr_v;
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/* check GPIO controller to check which pin triggered the interrupt */
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for (reg = 0; reg < lnw->chip.ngpio / 32; reg++) {
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gedr = (void __iomem *)(&lnw->reg_base->GEDR[reg]);
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gedr_v = readl(gedr);
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if (!gedr_v)
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continue;
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for (gpio = reg*32; gpio < reg*32+32; gpio++) {
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gedr_v = readl(gedr);
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if (gedr_v & BIT(gpio % 32)) {
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pr_debug("pin %d triggered\n", gpio);
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generic_handle_irq(lnw->irq_base + gpio);
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}
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}
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/* clear the edge detect status bit */
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writel(gedr_v, gedr);
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}
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desc->chip->eoi(irq);
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}
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static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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void *base;
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int i;
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resource_size_t start, len;
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struct lnw_gpio *lnw;
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u32 irq_base;
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u32 gpio_base;
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int retval = 0;
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retval = pci_enable_device(pdev);
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if (retval)
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goto done;
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retval = pci_request_regions(pdev, "langwell_gpio");
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if (retval) {
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dev_err(&pdev->dev, "error requesting resources\n");
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goto err2;
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}
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/* get the irq_base from bar1 */
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start = pci_resource_start(pdev, 1);
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len = pci_resource_len(pdev, 1);
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base = ioremap_nocache(start, len);
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if (!base) {
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dev_err(&pdev->dev, "error mapping bar1\n");
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goto err3;
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}
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irq_base = *(u32 *)base;
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gpio_base = *((u32 *)base + 1);
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/* release the IO mapping, since we already get the info from bar1 */
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iounmap(base);
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/* get the register base from bar0 */
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start = pci_resource_start(pdev, 0);
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len = pci_resource_len(pdev, 0);
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base = ioremap_nocache(start, len);
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if (!base) {
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dev_err(&pdev->dev, "error mapping bar0\n");
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retval = -EFAULT;
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goto err3;
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}
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lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
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if (!lnw) {
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dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
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retval = -ENOMEM;
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goto err4;
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}
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lnw->reg_base = base;
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lnw->irq_base = irq_base;
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lnw->chip.label = dev_name(&pdev->dev);
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lnw->chip.direction_input = lnw_gpio_direction_input;
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lnw->chip.direction_output = lnw_gpio_direction_output;
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lnw->chip.get = lnw_gpio_get;
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lnw->chip.set = lnw_gpio_set;
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lnw->chip.to_irq = lnw_gpio_to_irq;
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lnw->chip.base = gpio_base;
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lnw->chip.ngpio = 64;
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lnw->chip.can_sleep = 0;
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pci_set_drvdata(pdev, lnw);
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retval = gpiochip_add(&lnw->chip);
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if (retval) {
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dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
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goto err5;
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}
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set_irq_data(pdev->irq, lnw);
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set_irq_chained_handler(pdev->irq, lnw_irq_handler);
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for (i = 0; i < lnw->chip.ngpio; i++) {
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set_irq_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
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handle_simple_irq, "demux");
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set_irq_chip_data(i + lnw->irq_base, lnw);
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}
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spin_lock_init(&lnw->lock);
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goto done;
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err5:
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kfree(lnw);
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err4:
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iounmap(base);
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err3:
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pci_release_regions(pdev);
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err2:
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pci_disable_device(pdev);
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done:
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return retval;
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}
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static struct pci_driver lnw_gpio_driver = {
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.name = "langwell_gpio",
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.id_table = lnw_gpio_ids,
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.probe = lnw_gpio_probe,
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};
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static int __init lnw_gpio_init(void)
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{
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return pci_register_driver(&lnw_gpio_driver);
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}
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device_initcall(lnw_gpio_init);
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