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pata_hpt366: fix timing register documentation

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The comment in the driver actually describes HPT37x's timing register layout,
which is different from HPT36x.  Fix it and reformat the comment, while at it.

Bump the driver version, accounting for several patches that forgot to do it.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Sergei Shtylyov 2009-11-25 00:17:31 +04:00 committed by Jeff Garzik
parent 9cd13bdbae
commit 82beb5d894
1 changed files with 14 additions and 16 deletions
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30
drivers/ata/pata_hpt366.c
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@ -27,7 +27,7 @@
#include <linux/libata.h>
#define DRV_NAME "pata_hpt366"
#define DRV_VERSION "0.6.2"
#define DRV_VERSION "0.6.7"
struct hpt_clock {
u8 xfer_mode;
@ -36,24 +36,22 @@ struct hpt_clock {
/* key for bus clock timings
* bit
* 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
* DMA. cycles = value + 1
* 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
* DMA. cycles = value + 1
* 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
* cycles = value + 1
* 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
* cycles = value + 1
* 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
* register access.
* 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
* 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
* register access.
* 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
* during task file register access.
* 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
* xfer.
* 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
* 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
* 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
* 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
* register access.
* 28 UDMA enable
* 29 DMA enable
* 30 PIO_MST enable. if set, the chip is in bus master mode during
* PIO.
* 28 UDMA enable.
* 29 DMA enable.
* 30 PIO_MST enable. If set, the chip is in bus master mode during
* PIO xfer.
* 31 FIFO enable.
*/