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[ARM] 5092/1: Fix the I-cache invalidation on ARMv6 and later CPUs
This patch adds the I-cache invalidation in update_mmu_cache if the corresponding vma is marked as executable. It also invalidates the I-cache if a thread migrates to a CPU it never ran on. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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4 changed files with 18 additions and 0 deletions
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@ -144,13 +144,17 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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page = pfn_to_page(pfn);
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mapping = page_mapping(page);
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if (mapping) {
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#ifndef CONFIG_SMP
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int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
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if (dirty)
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__flush_dcache_page(mapping, page);
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#endif
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if (cache_is_vivt())
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make_coherent(mapping, vma, addr, pfn);
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else if (vma->vm_flags & VM_EXEC)
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__flush_icache_all();
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}
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}
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@ -199,6 +199,8 @@ void flush_dcache_page(struct page *page)
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__flush_dcache_page(mapping, page);
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if (mapping && cache_is_vivt())
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__flush_dcache_aliases(mapping, page);
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else if (mapping)
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__flush_icache_all();
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}
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}
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EXPORT_SYMBOL(flush_dcache_page);
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@ -410,6 +410,13 @@ extern void flush_dcache_page(struct page *);
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extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
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static inline void __flush_icache_all(void)
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{
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asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
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:
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: "r" (0));
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}
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#define ARCH_HAS_FLUSH_ANON_PAGE
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static inline void flush_anon_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vmaddr)
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@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
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#ifdef CONFIG_MMU
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unsigned int cpu = smp_processor_id();
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#ifdef CONFIG_SMP
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/* check for possible thread migration */
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if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask))
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__flush_icache_all();
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#endif
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if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
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check_context(next);
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cpu_switch_mm(next->pgd, next);
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