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MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors.
Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
92078e0618
commit
82622284dd
5 changed files with 68 additions and 14 deletions
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@ -1427,6 +1427,9 @@ config CPU_SUPPORTS_64BIT_KERNEL
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bool
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config CPU_SUPPORTS_HUGEPAGES
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bool
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config MIPS_PGD_C0_CONTEXT
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bool
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default y if 64BIT && CPU_MIPSR2
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#
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# Set to y for ptrace access to watch registers.
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@ -24,6 +24,33 @@
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#endif /* SMTC */
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#include <asm-generic/mm_hooks.h>
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#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
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tlbmiss_handler_setup_pgd((unsigned long)(pgd))
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static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
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{
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/* Check for swapper_pg_dir and convert to physical address. */
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if ((pgd & CKSEG3) == CKSEG0)
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pgd = CPHYSADDR(pgd);
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write_c0_context(pgd << 11);
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}
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#define TLBMISS_HANDLER_SETUP() \
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do { \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
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write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
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} while (0)
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static inline unsigned long get_current_pgd(void)
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{
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return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
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}
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#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
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/*
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* For the fast tlb miss handlers, we keep a per cpu array of pointers
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* to the current pgd for each processor. Also, the proc. id is stuffed
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@ -46,7 +73,7 @@ extern unsigned long pgd_current[];
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back_to_back_c0_hazard(); \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
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#endif
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define ASID_INC 0x40
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@ -87,15 +87,19 @@
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#ifdef CONFIG_SMP
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#ifdef CONFIG_MIPS_MT_SMTC
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#define PTEBASE_SHIFT 19 /* TCBIND */
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#define CPU_ID_REG CP0_TCBIND
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#define CPU_ID_MFC0 mfc0
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#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
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#define PTEBASE_SHIFT 48 /* XCONTEXT */
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#define CPU_ID_REG CP0_XCONTEXT
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#define CPU_ID_MFC0 MFC0
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#else
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#define PTEBASE_SHIFT 23 /* CONTEXT */
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#define CPU_ID_REG CP0_CONTEXT
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#define CPU_ID_MFC0 MFC0
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#endif
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.macro get_saved_sp /* SMP variation */
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#ifdef CONFIG_MIPS_MT_SMTC
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mfc0 k0, CP0_TCBIND
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#else
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MFC0 k0, CP0_CONTEXT
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#endif
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CPU_ID_MFC0 k0, CPU_ID_REG
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#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
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lui k1, %hi(kernelsp)
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#else
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@ -111,11 +115,7 @@
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.endm
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.macro set_saved_sp stackp temp temp2
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#ifdef CONFIG_MIPS_MT_SMTC
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mfc0 \temp, CP0_TCBIND
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#else
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MFC0 \temp, CP0_CONTEXT
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#endif
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CPU_ID_MFC0 \temp, CPU_ID_REG
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LONG_SRL \temp, PTEBASE_SHIFT
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LONG_S \stackp, kernelsp(\temp)
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.endm
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@ -462,7 +462,9 @@ void __init_refok free_initmem(void)
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__pa_symbol(&__init_end));
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}
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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unsigned long pgd_current[NR_CPUS];
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#endif
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/*
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* On 64-bit we've got three-level pagetables with a slightly
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* different layout ...
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@ -160,6 +160,12 @@ static u32 tlb_handler[128] __cpuinitdata;
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static struct uasm_label labels[128] __cpuinitdata;
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static struct uasm_reloc relocs[128] __cpuinitdata;
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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/*
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* CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
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* we cannot do r3000 under these circumstances.
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*/
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/*
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* The R3000 TLB handler is simple.
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*/
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@ -199,6 +205,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
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dump_handler((u32 *)ebase, 32);
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}
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
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/*
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* The R4000 TLB handler is much more complicated. We have two
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@ -497,8 +504,9 @@ static void __cpuinit
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build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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unsigned int tmp, unsigned int ptr)
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{
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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long pgdc = (long)pgd_current;
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#endif
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/*
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* The vmalloc handling is not in the hotpath.
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*/
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@ -506,7 +514,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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uasm_il_bltz(p, r, tmp, label_vmalloc);
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/* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
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#ifdef CONFIG_SMP
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#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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/*
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* &pgd << 11 stored in CONTEXT [23..63].
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*/
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UASM_i_MFC0(p, ptr, C0_CONTEXT);
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uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
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uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
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uasm_i_drotr(p, ptr, ptr, 11);
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#elif defined(CONFIG_SMP)
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# ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC uses TCBind value as "CPU" index
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@ -520,7 +536,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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*/
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uasm_i_dmfc0(p, ptr, C0_CONTEXT);
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uasm_i_dsrl(p, ptr, ptr, 23);
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#endif
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# endif
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UASM_i_LA_mostly(p, tmp, pgdc);
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uasm_i_daddu(p, ptr, ptr, tmp);
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uasm_i_dmfc0(p, tmp, C0_BADVADDR);
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@ -1033,6 +1049,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
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iPTE_LW(p, pte, ptr);
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}
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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/*
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* R3000 style TLB load/store/modify handlers.
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*/
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@ -1184,6 +1201,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
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dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
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}
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
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/*
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* R4000 style TLB load/store/modify handlers.
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@ -1400,6 +1418,7 @@ void __cpuinit build_tlb_refill_handler(void)
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case CPU_TX3912:
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case CPU_TX3922:
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case CPU_TX3927:
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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build_r3000_tlb_refill_handler();
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if (!run_once) {
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build_r3000_tlb_load_handler();
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@ -1407,6 +1426,9 @@ void __cpuinit build_tlb_refill_handler(void)
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build_r3000_tlb_modify_handler();
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run_once++;
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}
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#else
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panic("No R3000 TLB refill handler");
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#endif
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break;
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case CPU_R6000:
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