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crypto: talitos - add support for 36 bit addressing
Enabling extended addressing in the h/w requires we always assign the extended address component (eptr) of the talitos h/w pointer. This is for e500 based platforms with large memories. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Kim Phillips
Herbert Xu
parent
4b99262881
commit
81eb024c7e
2 changed files with 41 additions and 29 deletions
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@ -146,6 +146,12 @@ struct talitos_private {
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#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
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#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
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static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
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{
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talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
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talitos_ptr->eptr = cpu_to_be32(upper_32_bits(dma_addr));
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}
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/*
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* map virtual single (contiguous) pointer to h/w descriptor pointer
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*/
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@ -155,8 +161,10 @@ static void map_single_talitos_ptr(struct device *dev,
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unsigned char extent,
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enum dma_data_direction dir)
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{
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dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
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talitos_ptr->len = cpu_to_be16(len);
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talitos_ptr->ptr = cpu_to_be32(dma_map_single(dev, data, len, dir));
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to_talitos_ptr(talitos_ptr, dma_addr);
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talitos_ptr->j_extent = extent;
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}
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@ -187,9 +195,9 @@ static int reset_channel(struct device *dev, int ch)
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return -EIO;
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}
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/* set done writeback and IRQ */
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setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_CDWE |
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TALITOS_CCCR_LO_CDIE);
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/* set 36-bit addressing, done writeback enable and done IRQ enable */
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setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
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TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
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/* and ICCR writeback, if available */
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if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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@ -312,7 +320,10 @@ static int talitos_submit(struct device *dev, struct talitos_desc *desc,
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/* GO! */
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wmb();
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out_be32(priv->reg + TALITOS_FF_LO(ch), request->dma_desc);
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out_be32(priv->reg + TALITOS_FF(ch),
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cpu_to_be32(upper_32_bits(request->dma_desc)));
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out_be32(priv->reg + TALITOS_FF_LO(ch),
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cpu_to_be32(lower_32_bits(request->dma_desc)));
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spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
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@ -934,7 +945,7 @@ static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
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int n_sg = sg_count;
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while (n_sg--) {
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link_tbl_ptr->ptr = cpu_to_be32(sg_dma_address(sg));
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to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
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link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
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link_tbl_ptr->j_extent = 0;
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link_tbl_ptr++;
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@ -1009,7 +1020,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
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edesc->src_is_chained);
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if (sg_count == 1) {
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desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
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to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
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} else {
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sg_link_tbl_len = cryptlen;
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@ -1020,14 +1031,14 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
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&edesc->link_tbl[0]);
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if (sg_count > 1) {
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desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
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desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
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to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
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dma_sync_single_for_device(dev, edesc->dma_link_tbl,
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edesc->dma_len,
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DMA_BIDIRECTIONAL);
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} else {
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/* Only one segment now, so no link tbl needed */
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desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->
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src));
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to_talitos_ptr(&desc->ptr[4],
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sg_dma_address(areq->src));
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}
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}
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@ -1042,14 +1053,14 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
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edesc->dst_is_chained);
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if (sg_count == 1) {
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desc->ptr[5].ptr = cpu_to_be32(sg_dma_address(areq->dst));
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to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
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} else {
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struct talitos_ptr *link_tbl_ptr =
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&edesc->link_tbl[edesc->src_nents + 1];
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desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
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edesc->dma_link_tbl +
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edesc->src_nents + 1);
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to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
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(edesc->src_nents + 1) *
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sizeof(struct talitos_ptr));
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sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
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link_tbl_ptr);
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@ -1062,11 +1073,9 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
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link_tbl_ptr->len = cpu_to_be16(authsize);
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/* icv data follows link tables */
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link_tbl_ptr->ptr = cpu_to_be32((struct talitos_ptr *)
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edesc->dma_link_tbl +
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edesc->src_nents +
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edesc->dst_nents + 2);
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to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
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(edesc->src_nents + edesc->dst_nents + 2) *
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sizeof(struct talitos_ptr));
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desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
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dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
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edesc->dma_len, DMA_BIDIRECTIONAL);
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@ -1341,7 +1350,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
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/* first DWORD empty */
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desc->ptr[0].len = 0;
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desc->ptr[0].ptr = 0;
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to_talitos_ptr(&desc->ptr[0], 0);
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desc->ptr[0].j_extent = 0;
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/* cipher iv */
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@ -1365,20 +1374,20 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
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edesc->src_is_chained);
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if (sg_count == 1) {
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desc->ptr[3].ptr = cpu_to_be32(sg_dma_address(areq->src));
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to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
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} else {
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sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
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&edesc->link_tbl[0]);
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if (sg_count > 1) {
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to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
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desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
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desc->ptr[3].ptr = cpu_to_be32(edesc->dma_link_tbl);
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dma_sync_single_for_device(dev, edesc->dma_link_tbl,
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edesc->dma_len,
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DMA_BIDIRECTIONAL);
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} else {
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/* Only one segment now, so no link tbl needed */
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desc->ptr[3].ptr = cpu_to_be32(sg_dma_address(areq->
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src));
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to_talitos_ptr(&desc->ptr[3],
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sg_dma_address(areq->src));
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}
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}
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@ -1393,15 +1402,15 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
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edesc->dst_is_chained);
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if (sg_count == 1) {
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desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->dst));
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to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
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} else {
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struct talitos_ptr *link_tbl_ptr =
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&edesc->link_tbl[edesc->src_nents + 1];
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to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
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(edesc->src_nents + 1) *
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sizeof(struct talitos_ptr));
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desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
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desc->ptr[4].ptr = cpu_to_be32((struct talitos_ptr *)
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edesc->dma_link_tbl +
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edesc->src_nents + 1);
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sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
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link_tbl_ptr);
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dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
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@ -1414,7 +1423,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
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/* last DWORD empty */
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desc->ptr[6].len = 0;
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desc->ptr[6].ptr = 0;
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to_talitos_ptr(&desc->ptr[6], 0);
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desc->ptr[6].j_extent = 0;
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ret = talitos_submit(dev, desc, callback, areq);
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@ -1898,6 +1907,8 @@ static int talitos_probe(struct of_device *ofdev,
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atomic_set(&priv->chan[i].submit_count,
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-(priv->chfifo_len - 1));
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dma_set_mask(dev, DMA_BIT_MASK(36));
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/* reset and initialize the h/w */
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err = init_device(dev);
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if (err) {
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@ -57,6 +57,7 @@
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#define TALITOS_CCCR_RESET 0x1 /* channel reset */
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#define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c)
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#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
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#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
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#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
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#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
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#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
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