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[WATCHDOG] davinci watchdog driver
Add watchdog support for TI Davinci DM644x/DM646x processors. Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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@ -203,6 +203,18 @@ config IOP_WATCHDOG
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operating as an Root Complex and/or Central Resource, the PCI-X
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and/or PCIe busses will also be reset. THIS IS A VERY BIG HAMMER.
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config DAVINCI_WATCHDOG
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tristate "DaVinci watchdog"
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depends on WATCHDOG && ARCH_DAVINCI
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help
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Say Y here if to include support for the watchdog timer
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in the DaVinci DM644x/DM646x processors.
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To compile this driver as a module, choose M here: the
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module will be called davinci_wdt.
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NOTE: once enabled, this timer cannot be disabled.
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Say N if you are unsure.
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# AVR32 Architecture
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config AT32AP700X_WDT
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@ -36,6 +36,7 @@ obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
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obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
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obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
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obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
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obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
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# AVR32 Architecture
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obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
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284
drivers/char/watchdog/davinci_wdt.c
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284
drivers/char/watchdog/davinci_wdt.c
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@ -0,0 +1,284 @@
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/*
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* drivers/char/watchdog/davinci_wdt.c
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*
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* Watchdog driver for DaVinci DM644x/DM646x processors
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <asm/hardware.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#define MODULE_NAME "DAVINCI-WDT: "
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#define DEFAULT_HEARTBEAT 60
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#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
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/* Timer register set definition */
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#define PID12 (0x0)
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#define EMUMGT (0x4)
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#define TIM12 (0x10)
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#define TIM34 (0x14)
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#define PRD12 (0x18)
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#define PRD34 (0x1C)
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#define TCR (0x20)
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#define TGCR (0x24)
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#define WDTCR (0x28)
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/* TCR bit definitions */
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#define ENAMODE12_DISABLED (0 << 6)
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#define ENAMODE12_ONESHOT (1 << 6)
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#define ENAMODE12_PERIODIC (2 << 6)
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/* TGCR bit definitions */
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#define TIM12RS_UNRESET (1 << 0)
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#define TIM34RS_UNRESET (1 << 1)
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#define TIMMODE_64BIT_WDOG (2 << 2)
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/* WDTCR bit definitions */
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#define WDEN (1 << 14)
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#define WDFLAG (1 << 15)
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#define WDKEY_SEQ0 (0xa5c6 << 16)
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#define WDKEY_SEQ1 (0xda7e << 16)
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static int heartbeat = DEFAULT_HEARTBEAT;
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static spinlock_t io_lock;
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static unsigned long wdt_status;
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#define WDT_IN_USE 0
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#define WDT_OK_TO_CLOSE 1
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#define WDT_REGION_INITED 2
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#define WDT_DEVICE_INITED 3
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static struct resource *wdt_mem;
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static void __iomem *wdt_base;
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static void wdt_service(void)
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{
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spin_lock(&io_lock);
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/* put watchdog in service state */
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davinci_writel(WDKEY_SEQ0, wdt_base + WDTCR);
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/* put watchdog in active state */
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davinci_writel(WDKEY_SEQ1, wdt_base + WDTCR);
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spin_unlock(&io_lock);
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}
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static void wdt_enable(void)
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{
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u32 tgcr;
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u32 timer_margin;
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spin_lock(&io_lock);
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/* disable, internal clock source */
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davinci_writel(0, wdt_base + TCR);
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/* reset timer, set mode to 64-bit watchdog, and unreset */
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davinci_writel(0, wdt_base + TGCR);
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tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
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davinci_writel(tgcr, wdt_base + TGCR);
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/* clear counter regs */
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davinci_writel(0, wdt_base + TIM12);
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davinci_writel(0, wdt_base + TIM34);
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/* set timeout period */
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timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff);
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davinci_writel(timer_margin, wdt_base + PRD12);
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timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32);
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davinci_writel(timer_margin, wdt_base + PRD34);
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/* enable run continuously */
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davinci_writel(ENAMODE12_PERIODIC, wdt_base + TCR);
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/* Once the WDT is in pre-active state write to
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* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
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* write protected (except for the WDKEY field)
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*/
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/* put watchdog in pre-active state */
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davinci_writel(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
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/* put watchdog in active state */
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davinci_writel(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
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spin_unlock(&io_lock);
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}
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static int davinci_wdt_open(struct inode *inode, struct file *file)
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{
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if (test_and_set_bit(WDT_IN_USE, &wdt_status))
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return -EBUSY;
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wdt_enable();
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return nonseekable_open(inode, file);
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}
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static ssize_t
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davinci_wdt_write(struct file *file, const char *data, size_t len,
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loff_t *ppos)
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{
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/* Can't seek (pwrite) on this device */
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if (ppos != &file->f_pos)
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return -ESPIPE;
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if (len)
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wdt_service();
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return len;
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}
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static struct watchdog_info ident = {
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.options = WDIOF_CARDRESET | WDIOF_KEEPALIVEPING,
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.identity = "DaVinci Watchdog",
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};
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static int
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davinci_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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int ret = -ENOTTY;
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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ret = copy_to_user((struct watchdog_info *)arg, &ident,
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sizeof(ident)) ? -EFAULT : 0;
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break;
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case WDIOC_GETSTATUS:
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ret = put_user(0, (int *)arg);
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break;
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case WDIOC_GETTIMEOUT:
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ret = put_user(heartbeat, (int *)arg);
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break;
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case WDIOC_KEEPALIVE:
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wdt_service();
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ret = 0;
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break;
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}
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return ret;
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}
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static int davinci_wdt_release(struct inode *inode, struct file *file)
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{
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wdt_service();
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clear_bit(WDT_IN_USE, &wdt_status);
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return 0;
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}
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static const struct file_operations davinci_wdt_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = davinci_wdt_write,
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.ioctl = davinci_wdt_ioctl,
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.open = davinci_wdt_open,
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.release = davinci_wdt_release,
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};
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static struct miscdevice davinci_wdt_miscdev = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &davinci_wdt_fops,
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};
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static int davinci_wdt_probe(struct platform_device *pdev)
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{
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int ret = 0, size;
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struct resource *res;
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spin_lock_init(&io_lock);
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if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
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heartbeat = DEFAULT_HEARTBEAT;
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printk(KERN_INFO MODULE_NAME
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"DaVinci Watchdog Timer: heartbeat %d sec\n", heartbeat);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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printk(KERN_INFO MODULE_NAME
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"failed to get memory region resource\n");
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return -ENOENT;
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}
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size = res->end - res->start + 1;
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wdt_mem = request_mem_region(res->start, size, pdev->name);
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if (wdt_mem == NULL) {
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printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
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return -ENOENT;
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}
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wdt_base = (void __iomem *)(res->start);
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ret = misc_register(&davinci_wdt_miscdev);
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if (ret < 0) {
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printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
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release_resource(wdt_mem);
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kfree(wdt_mem);
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} else {
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set_bit(WDT_DEVICE_INITED, &wdt_status);
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}
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return ret;
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}
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static int davinci_wdt_remove(struct platform_device *pdev)
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{
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misc_deregister(&davinci_wdt_miscdev);
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if (wdt_mem) {
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release_resource(wdt_mem);
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kfree(wdt_mem);
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wdt_mem = NULL;
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}
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return 0;
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}
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static struct platform_driver platform_wdt_driver = {
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.driver = {
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.name = "watchdog",
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},
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.probe = davinci_wdt_probe,
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.remove = davinci_wdt_remove,
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};
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static int __init davinci_wdt_init(void)
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{
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return platform_driver_register(&platform_wdt_driver);
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}
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static void __exit davinci_wdt_exit(void)
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{
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return platform_driver_unregister(&platform_wdt_driver);
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}
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module_init(davinci_wdt_init);
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module_exit(davinci_wdt_exit);
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MODULE_AUTHOR("Texas Instruments");
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MODULE_DESCRIPTION("DaVinci Watchdog Driver");
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeat period in seconds from 1 to "
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__MODULE_STRING(MAX_HEARTBEAT) ", default "
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__MODULE_STRING(DEFAULT_HEARTBEAT));
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MODULE_LICENSE("GPL");
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MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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