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https://github.com/adulau/aha.git
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[SERIAL] sunzilog: Interrupt enable before ISR handler installed
This patch changes the interrupt enable sequence for the sunzilog driver so that interrupts are not enabled untill after the interrupt handler has been installed. If this is not done, some SS1 and SS2 sun4c systems panic on un-handled interrupt before the handler gets installed preventing boot. It also adds in support for the ESCC version of the zilog chips. The changes mean that the FIFO will be enabled for ESCC versions of the SCC UART. My interpretation of the SCC manual and the existing interrupt handler code is that it sould be able to make good use of the FIFO without issues. Signed-off-by: Mark Fortescue <mark@mtfhpc.demon.co.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mark Fortescue
David S. Miller
parent
ca3dd88e41
commit
7cc5c8559c
2 changed files with 122 additions and 35 deletions
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@ -92,6 +92,8 @@ struct uart_sunzilog_port {
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#define SUNZILOG_FLAG_REGS_HELD 0x00000040
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#define SUNZILOG_FLAG_TX_STOPPED 0x00000080
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#define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
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#define SUNZILOG_FLAG_ESCC 0x00000200
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#define SUNZILOG_FLAG_ISR_HANDLER 0x00000400
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unsigned int cflag;
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@ -174,9 +176,11 @@ static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
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/* This function must only be called when the TX is not busy. The UART
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* port lock must be held and local interrupts disabled.
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*/
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static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
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static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
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{
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int i;
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int escc;
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unsigned char r15;
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/* Let pending transmits finish. */
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for (i = 0; i < 1000; i++) {
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@ -229,11 +233,25 @@ static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *
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write_zsreg(channel, R14, regs[R14]);
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/* External status interrupt control. */
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write_zsreg(channel, R15, regs[R15]);
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write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
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/* ESCC Extension Register */
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r15 = read_zsreg(channel, R15);
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if (r15 & 0x01) {
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write_zsreg(channel, R7, regs[R7p]);
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/* External status interrupt and FIFO control. */
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write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
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escc = 1;
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} else {
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/* Clear FIFO bit case it is an issue */
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regs[R15] &= ~FIFOEN;
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escc = 0;
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}
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/* Reset external status interrupts. */
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write_zsreg(channel, R0, RES_EXT_INT);
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write_zsreg(channel, R0, RES_EXT_INT);
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write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */
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write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
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/* Rewrite R3/R5, this time without enables masked. */
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write_zsreg(channel, R3, regs[R3]);
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@ -241,6 +259,8 @@ static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *
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/* Rewrite R1, this time without IRQ enabled masked. */
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write_zsreg(channel, R1, regs[R1]);
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return escc;
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}
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/* Reprogram the Zilog channel HW registers with the copies found in the
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@ -731,7 +751,7 @@ static void sunzilog_enable_ms(struct uart_port *port)
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up->curregs[R15] = new_reg;
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/* NOTE: Not subject to 'transmitter active' rule. */
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write_zsreg(channel, R15, up->curregs[R15]);
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write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
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}
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}
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@ -861,44 +881,44 @@ sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
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up->curregs[R14] = BRSRC | BRENAB;
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/* Character size, stop bits, and parity. */
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up->curregs[3] &= ~RxN_MASK;
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up->curregs[5] &= ~TxN_MASK;
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up->curregs[R3] &= ~RxN_MASK;
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up->curregs[R5] &= ~TxN_MASK;
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switch (cflag & CSIZE) {
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case CS5:
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up->curregs[3] |= Rx5;
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up->curregs[5] |= Tx5;
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up->curregs[R3] |= Rx5;
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up->curregs[R5] |= Tx5;
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up->parity_mask = 0x1f;
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break;
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case CS6:
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up->curregs[3] |= Rx6;
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up->curregs[5] |= Tx6;
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up->curregs[R3] |= Rx6;
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up->curregs[R5] |= Tx6;
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up->parity_mask = 0x3f;
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break;
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case CS7:
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up->curregs[3] |= Rx7;
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up->curregs[5] |= Tx7;
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up->curregs[R3] |= Rx7;
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up->curregs[R5] |= Tx7;
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up->parity_mask = 0x7f;
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break;
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case CS8:
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default:
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up->curregs[3] |= Rx8;
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up->curregs[5] |= Tx8;
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up->curregs[R3] |= Rx8;
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up->curregs[R5] |= Tx8;
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up->parity_mask = 0xff;
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break;
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};
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up->curregs[4] &= ~0x0c;
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up->curregs[R4] &= ~0x0c;
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if (cflag & CSTOPB)
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up->curregs[4] |= SB2;
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up->curregs[R4] |= SB2;
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else
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up->curregs[4] |= SB1;
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up->curregs[R4] |= SB1;
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if (cflag & PARENB)
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up->curregs[4] |= PAR_ENAB;
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up->curregs[R4] |= PAR_ENAB;
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else
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up->curregs[4] &= ~PAR_ENAB;
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up->curregs[R4] &= ~PAR_ENAB;
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if (!(cflag & PARODD))
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up->curregs[4] |= PAR_EVEN;
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up->curregs[R4] |= PAR_EVEN;
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else
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up->curregs[4] &= ~PAR_EVEN;
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up->curregs[R4] &= ~PAR_EVEN;
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up->port.read_status_mask = Rx_OVR;
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if (iflag & INPCK)
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@ -952,7 +972,9 @@ sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
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static const char *sunzilog_type(struct uart_port *port)
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{
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return "zs";
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struct uart_sunzilog_port *up = UART_ZILOG(port);
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return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
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}
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/* We do not request/release mappings of the registers here, this
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@ -1170,7 +1192,7 @@ static int __init sunzilog_console_setup(struct console *con, char *options)
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spin_lock_irqsave(&up->port.lock, flags);
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up->curregs[R15] = BRKIE;
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up->curregs[R15] |= BRKIE;
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sunzilog_convert_to_zs(up, con->cflag, 0, brg);
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sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
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@ -1229,7 +1251,7 @@ static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channe
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baud = 4800;
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}
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up->curregs[R15] = BRKIE;
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up->curregs[R15] |= BRKIE;
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brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
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sunzilog_convert_to_zs(up, up->cflag, 0, brg);
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sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
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@ -1283,8 +1305,18 @@ static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
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if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
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SUNZILOG_FLAG_CONS_MOUSE)) {
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up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
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up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
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up->curregs[R3] = RxENAB | Rx8;
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up->curregs[R5] = TxENAB | Tx8;
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up->curregs[R6] = 0x00; /* SDLC Address */
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up->curregs[R7] = 0x7E; /* SDLC Flag */
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up->curregs[R9] = NV;
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up->curregs[R7p] = 0x00;
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sunzilog_init_kbdms(up, up->port.line);
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up->curregs[R9] |= (NV | MIE);
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/* Only enable interrupts if an ISR handler available */
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if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
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up->curregs[R9] |= MIE;
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write_zsreg(channel, R9, up->curregs[R9]);
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} else {
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/* Normal serial TTY. */
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@ -1293,7 +1325,9 @@ static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
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up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
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up->curregs[R3] = RxENAB | Rx8;
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up->curregs[R5] = TxENAB | Tx8;
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up->curregs[R9] = NV | MIE;
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up->curregs[R6] = 0x00; /* SDLC Address */
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up->curregs[R7] = 0x7E; /* SDLC Flag */
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up->curregs[R9] = NV;
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up->curregs[R10] = NRZ;
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up->curregs[R11] = TCBR | RCBR;
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baud = 9600;
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@ -1301,7 +1335,14 @@ static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
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up->curregs[R12] = (brg & 0xff);
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up->curregs[R13] = (brg >> 8) & 0xff;
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up->curregs[R14] = BRSRC | BRENAB;
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__load_zsregs(channel, up->curregs);
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up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
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up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
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if (__load_zsregs(channel, up->curregs)) {
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up->flags |= SUNZILOG_FLAG_ESCC;
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}
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/* Only enable interrupts if an ISR handler available */
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if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
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up->curregs[R9] |= MIE;
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write_zsreg(channel, R9, up->curregs[R9]);
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}
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@ -1390,12 +1431,14 @@ static int __devinit zs_probe(struct of_device *op, const struct of_device_id *m
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return err;
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}
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} else {
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printk(KERN_INFO "%s: Keyboard at MMIO %lx (irq = %d) "
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"is a zs\n",
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op->dev.bus_id, up[0].port.mapbase, op->irqs[0]);
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printk(KERN_INFO "%s: Mouse at MMIO %lx (irq = %d) "
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"is a zs\n",
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op->dev.bus_id, up[1].port.mapbase, op->irqs[0]);
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printk(KERN_INFO "%s: Keyboard at MMIO 0x%lx (irq = %d) "
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"is a %s\n",
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op->dev.bus_id, up[0].port.mapbase, op->irqs[0],
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sunzilog_type (&up[0].port));
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printk(KERN_INFO "%s: Mouse at MMIO 0x%lx (irq = %d) "
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"is a %s\n",
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op->dev.bus_id, up[1].port.mapbase, op->irqs[0],
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sunzilog_type (&up[1].port));
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}
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dev_set_drvdata(&op->dev, &up[0]);
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@ -1487,10 +1530,23 @@ static int __init sunzilog_init(void)
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goto out_unregister_uart;
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if (zilog_irq != -1) {
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struct uart_sunzilog_port *up = sunzilog_irq_chain;
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err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
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"zs", sunzilog_irq_chain);
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if (err)
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goto out_unregister_driver;
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/* Enable Interrupts */
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while (up) {
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struct zilog_channel __iomem *channel;
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/* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
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channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
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up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
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up->curregs[R9] |= MIE;
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write_zsreg(channel, R9, up->curregs[R9]);
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up = up->next;
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}
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}
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out:
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@ -1515,6 +1571,20 @@ static void __exit sunzilog_exit(void)
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of_unregister_driver(&zs_driver);
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if (zilog_irq != -1) {
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struct uart_sunzilog_port *up = sunzilog_irq_chain;
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/* Disable Interrupts */
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while (up) {
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struct zilog_channel __iomem *channel;
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/* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
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channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
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up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
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up->curregs[R9] &= ~MIE;
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write_zsreg(channel, R9, up->curregs[R9]);
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up = up->next;
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}
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free_irq(zilog_irq, sunzilog_irq_chain);
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zilog_irq = -1;
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}
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@ -13,7 +13,8 @@ struct zilog_layout {
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struct zilog_channel channelA;
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};
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#define NUM_ZSREGS 16
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#define NUM_ZSREGS 17
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#define R7p 16 /* Written as R7 with P15 bit 0 set */
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/* Conversion routines to/from brg time constants from/to bits
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* per second.
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@ -127,6 +128,15 @@ struct zilog_layout {
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/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
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/* Write Register 7' (ESCC Only) */
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#define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */
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#define AUTO_EOM_RST 2 /* Automatic EOM Reset */
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#define AUTOnRTS 4 /* Automatic /RTS pin deactivation */
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#define RxFIFO_LVL 8 /* Receive FIFO interrupt level */
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#define nDTRnREQ 0x10 /* /DTR/REQ timing */
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#define TxFIFO_LVL 0x20 /* Transmit FIFO interrupt level */
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#define EXT_RD_EN 0x40 /* Extended read register enable */
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/* Write Register 8 (transmit buffer) */
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/* Write Register 9 (Master interrupt control) */
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@ -135,6 +145,7 @@ struct zilog_layout {
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#define DLC 4 /* Disable Lower Chain */
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#define MIE 8 /* Master Interrupt Enable */
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#define STATHI 0x10 /* Status high */
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#define SWIACK 0x20 /* Software Interrupt Ack (not on NMOS) */
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#define NORESET 0 /* No reset on write to R9 */
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#define CHRB 0x40 /* Reset channel B */
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#define CHRA 0x80 /* Reset channel A */
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@ -187,7 +198,9 @@ struct zilog_layout {
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#define SNRZI 0xe0 /* Set NRZI mode */
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/* Write Register 15 (external/status interrupt control) */
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#define WR7pEN 1 /* WR7' Enable (ESCC only) */
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#define ZCIE 2 /* Zero count IE */
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#define FIFOEN 4 /* FIFO Enable (ESCC only) */
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#define DCDIE 8 /* DCD IE */
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#define SYNCIE 0x10 /* Sync/hunt IE */
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#define CTSIE 0x20 /* CTS IE */
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@ -241,6 +254,10 @@ struct zilog_layout {
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#define CHATxIP 0x10 /* Channel A Tx IP */
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#define CHARxIP 0x20 /* Channel A Rx IP */
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/* Read Register 6 (LSB frame byte count [Not on NMOS]) */
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/* Read Register 7 (MSB frame byte count and FIFO status [Not on NMOS]) */
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/* Read Register 8 (receive data register) */
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/* Read Register 10 (misc status bits) */
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