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davinci: Add NOR flash support for da850/omap-l138
This patch adds platform data for the 8MB NOR flash found on da850/omap-l138 EVM. Both NOR and NAND can co-exist on da850/omap-l138 as they are using different chip selects. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sudhakar Rajashekhara
Kevin Hilman
parent
38beb929f2
commit
7c5ec6095a
4 changed files with 145 additions and 0 deletions
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@ -22,6 +22,7 @@
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -41,6 +42,39 @@
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#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
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#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
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static struct mtd_partition da850_evm_norflash_partition[] = {
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{
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.name = "NOR filesystem",
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.offset = 0,
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.size = MTDPART_SIZ_FULL,
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.mask_flags = 0,
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},
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};
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static struct physmap_flash_data da850_evm_norflash_data = {
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.width = 2,
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.parts = da850_evm_norflash_partition,
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.nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
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};
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static struct resource da850_evm_norflash_resource[] = {
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{
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.start = DA8XX_AEMIF_CS2_BASE,
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.end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device da850_evm_norflash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &da850_evm_norflash_data,
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},
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.num_resources = 1,
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.resource = da850_evm_norflash_resource,
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};
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/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
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* (128K blocks). It may be used instead of the (default) SPI flash
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* to boot, using TI's tools to install the secondary boot loader
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@ -120,6 +154,7 @@ static struct davinci_uart_config da850_evm_uart_config __initdata = {
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static struct platform_device *da850_evm_devices[] __initdata = {
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&da850_evm_nandflash_device,
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&da850_evm_norflash_device,
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};
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/* davinci da850 evm audio machine driver */
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@ -192,6 +227,23 @@ static int da850_lcd_hw_init(void)
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return 0;
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}
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#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
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#define DA8XX_AEMIF_ASIZE_16BIT 0x1
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static void __init da850_evm_init_nor(void)
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{
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void __iomem *aemif_addr;
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aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
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/* Configure data bus width of CS2 to 16 bit */
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writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
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DA8XX_AEMIF_ASIZE_16BIT,
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aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
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iounmap(aemif_addr);
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}
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static __init void da850_evm_init(void)
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{
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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@ -202,6 +254,13 @@ static __init void da850_evm_init(void)
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pr_warning("da850_evm_init: nand mux setup failed: %d\n",
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ret);
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ret = da8xx_pinmux_setup(da850_nor_pins);
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if (ret)
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pr_warning("da850_evm_init: nor mux setup failed: %d\n",
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ret);
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da850_evm_init_nor();
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platform_add_devices(da850_evm_devices,
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ARRAY_SIZE(da850_evm_devices));
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@ -471,6 +471,40 @@ static const struct mux_config da850_pins[] = {
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MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
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MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
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MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
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MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
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MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
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MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
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MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
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MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
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MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
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MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
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MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
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MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
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MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
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MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
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MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
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MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
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MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
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MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
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MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
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MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
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MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
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MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
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MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
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MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
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MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
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MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
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MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
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MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
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MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
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MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
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MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
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MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
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MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
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MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
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MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
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MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
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MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
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/* GPIO function */
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MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
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MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false)
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@ -545,6 +579,22 @@ const short da850_nand_pins[] __initdata = {
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-1
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};
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const short da850_nor_pins[] __initdata = {
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DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
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DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
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DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
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DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
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DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
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DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
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DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
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DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
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DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
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DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
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DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
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DA850_EMA_A_22, DA850_EMA_A_23,
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-1
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};
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/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
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static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
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[IRQ_DA8XX_COMMTX] = 7,
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@ -40,6 +40,7 @@
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#define DA8XX_PSC1_BASE 0x01e27000
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#define DA8XX_LCD_CNTRL_BASE 0x01e13000
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#define DA8XX_MMCSD0_BASE 0x01c40000
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#define DA8XX_AEMIF_CS2_BASE 0x60000000
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#define DA8XX_AEMIF_CS3_BASE 0x62000000
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#define DA8XX_AEMIF_CTL_BASE 0x68000000
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@ -113,6 +114,7 @@ extern const short da850_mcasp_pins[];
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extern const short da850_lcdcntl_pins[];
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extern const short da850_mmcsd0_pins[];
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extern const short da850_nand_pins[];
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extern const short da850_nor_pins[];
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int da8xx_pinmux_setup(const short pins[]);
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@ -821,6 +821,40 @@ enum davinci_da850_index {
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DA850_NEMA_CS_4,
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DA850_NEMA_WE,
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DA850_NEMA_OE,
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DA850_EMA_D_15,
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DA850_EMA_D_14,
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DA850_EMA_D_13,
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DA850_EMA_D_12,
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DA850_EMA_D_11,
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DA850_EMA_D_10,
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DA850_EMA_D_9,
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DA850_EMA_D_8,
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DA850_EMA_A_0,
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DA850_EMA_A_3,
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DA850_EMA_A_4,
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DA850_EMA_A_5,
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DA850_EMA_A_6,
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DA850_EMA_A_7,
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DA850_EMA_A_8,
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DA850_EMA_A_9,
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DA850_EMA_A_10,
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DA850_EMA_A_11,
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DA850_EMA_A_12,
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DA850_EMA_A_13,
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DA850_EMA_A_14,
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DA850_EMA_A_15,
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DA850_EMA_A_16,
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DA850_EMA_A_17,
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DA850_EMA_A_18,
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DA850_EMA_A_19,
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DA850_EMA_A_20,
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DA850_EMA_A_21,
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DA850_EMA_A_22,
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DA850_EMA_A_23,
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DA850_EMA_BA_1,
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DA850_EMA_CLK,
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DA850_EMA_WAIT_1,
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DA850_NEMA_CS_2,
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/* GPIO function */
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DA850_GPIO2_15,
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