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[PATCH] ppc64: cleanup SPR definitions
There are a bunch of irrelevant SPR definitions in asm/processer.h. Cut them down a bit, also add a DABR_TRANSLATION define which will be used shortly. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Anton Blanchard
Linus Torvalds
parent
7e3b11a9be
commit
79f1248962
1 changed files with 1 additions and 158 deletions
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@ -120,103 +120,18 @@
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/* Special Purpose Registers (SPRNs)*/
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#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
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#define SPRN_CTR 0x009 /* Count Register */
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#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
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#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
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#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
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#define DABR_TRANSLATION (1UL << 2)
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#define SPRN_DAR 0x013 /* Data Address Register */
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#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
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#define DBCR_EDM 0x80000000
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#define DBCR_IDM 0x40000000
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#define DBCR_RST(x) (((x) & 0x3) << 28)
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#define DBCR_RST_NONE 0
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#define DBCR_RST_CORE 1
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#define DBCR_RST_CHIP 2
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#define DBCR_RST_SYSTEM 3
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#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
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#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
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#define DBCR_EDE 0x02000000 /* Exception Debug Event */
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#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
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#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
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#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
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#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
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#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
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#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
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#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
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#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
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#define DAC_BYTE 0
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#define DAC_HALF 1
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#define DAC_WORD 2
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#define DAC_QUAD 3
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#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
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#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
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#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
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#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
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#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
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#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
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#define DBCR_SIA 0x00000008 /* Second IAC Enable */
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#define DBCR_SDA 0x00000004 /* Second DAC Enable */
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#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
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#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
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#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
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#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
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#define SPRN_DBSR 0x3F0 /* Debug Status Register */
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#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
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#define DCCR_NOCACHE 0 /* Noncacheable */
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#define DCCR_CACHE 1 /* Cacheable */
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#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
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#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
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#define DCWR_COPY 0 /* Copy-back */
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#define DCWR_WRITE 1 /* Write-through */
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#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
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#define SPRN_DEC 0x016 /* Decrement Register */
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#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
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#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
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#define DSISR_NOHPTE 0x40000000 /* no translation found */
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#define DSISR_PROTFAULT 0x08000000 /* protection fault */
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#define DSISR_ISSTORE 0x02000000 /* access was a store */
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#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
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#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
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#define SPRN_EAR 0x11A /* External Address Register */
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#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
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#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
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#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
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#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
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#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
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#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
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#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
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#define ESR_PTR 0x02000000 /* Program Exception - Trap */
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#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
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#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
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#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
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#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
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#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
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#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
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#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
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#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
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#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
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#define HID0_SBCLK (1<<27)
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#define HID0_EICE (1<<26)
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#define HID0_ECLK (1<<25)
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#define HID0_PAR (1<<24)
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#define HID0_DOZE (1<<23)
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#define HID0_NAP (1<<22)
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#define HID0_SLEEP (1<<21)
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#define HID0_DPM (1<<20)
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#define HID0_ICE (1<<15) /* Instruction Cache Enable */
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#define HID0_DCE (1<<14) /* Data Cache Enable */
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#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
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#define HID0_DLOCK (1<<12) /* Data Cache Lock */
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#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
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#define HID0_DCI (1<<10) /* Data Cache Invalidate */
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#define HID0_SPD (1<<9) /* Speculative disable */
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#define HID0_SGE (1<<7) /* Store Gathering Enable */
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#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
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#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
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#define HID0_ABE (1<<3) /* Address Broadcast Enable */
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#define HID0_BHTE (1<<2) /* Branch History Table Enable */
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#define HID0_BTCD (1<<1) /* Branch target cache disable */
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#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */
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#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
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#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
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@ -225,23 +140,8 @@
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#define SPRN_HID5 0x3F6 /* 970 HID5 */
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#define SPRN_TSC 0x3FD /* Thread switch control */
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#define SPRN_TST 0x3FC /* Thread switch timeout */
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#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
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#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
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#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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#define ICCR_NOCACHE 0 /* Noncacheable */
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#define ICCR_CACHE 1 /* Cacheable */
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#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
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#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
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#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
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#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
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#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
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#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
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#define SPRN_LR 0x008 /* Link Register */
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#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
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#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
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#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
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#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
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#define SPRN_PID 0x3B1 /* Process ID */
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#define SPRN_PIR 0x3FF /* Processor Identification Register */
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#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
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#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */
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@ -249,9 +149,6 @@
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#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
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#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
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#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
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#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
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#define SGR_NORMAL 0
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#define SGR_GUARDED 1
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#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
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#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
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#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
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@ -264,49 +161,8 @@
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#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */
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#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */
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#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
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#define SPRN_TCR 0x3DA /* Timer Control Register */
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#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
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#define WP_2_17 0 /* 2^17 clocks */
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#define WP_2_21 1 /* 2^21 clocks */
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#define WP_2_25 2 /* 2^25 clocks */
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#define WP_2_29 3 /* 2^29 clocks */
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#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
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#define WRC_NONE 0 /* No reset will occur */
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#define WRC_CORE 1 /* Core reset will occur */
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#define WRC_CHIP 2 /* Chip reset will occur */
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#define WRC_SYSTEM 3 /* System reset will occur */
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#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
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#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
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#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
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#define FP_2_9 0 /* 2^9 clocks */
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#define FP_2_13 1 /* 2^13 clocks */
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#define FP_2_17 2 /* 2^17 clocks */
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#define FP_2_21 3 /* 2^21 clocks */
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#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
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#define TCR_ARE 0x00400000 /* Auto Reload Enable */
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#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
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#define THRM1_TIN (1<<0)
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#define THRM1_TIV (1<<1)
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#define THRM1_THRES (0x7f<<2)
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#define THRM1_TID (1<<29)
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#define THRM1_TIE (1<<30)
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#define THRM1_V (1<<31)
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#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
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#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
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#define THRM3_E (1<<31)
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#define SPRN_TSR 0x3D8 /* Timer Status Register */
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#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
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#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
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#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
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#define WRS_NONE 0 /* No WDT reset occurred */
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#define WRS_CORE 1 /* WDT forced core reset */
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#define WRS_CHIP 2 /* WDT forced chip reset */
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#define WRS_SYSTEM 3 /* WDT forced system reset */
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#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
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#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
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#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
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#define SPRN_XER 0x001 /* Fixed Point Exception Register */
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#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
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#define SPRN_VRSAVE 0x100 /* Vector save */
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/* Performance monitor SPRs */
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@ -352,28 +208,19 @@
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#define CTR SPRN_CTR /* Counter Register */
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#define DAR SPRN_DAR /* Data Address Register */
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#define DABR SPRN_DABR /* Data Address Breakpoint Register */
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#define DCMP SPRN_DCMP /* Data TLB Compare Register */
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#define DEC SPRN_DEC /* Decrement Register */
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#define DMISS SPRN_DMISS /* Data TLB Miss Register */
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#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
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#define EAR SPRN_EAR /* External Address Register */
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#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
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#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
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#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
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#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */
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#define NIADORM SPRN_NIADORM /* NIA Dormant Register */
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#define TSC SPRN_TSC /* Thread switch control */
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#define TST SPRN_TST /* Thread switch timeout */
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#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
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#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
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#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
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#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
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#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
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#define __LR SPRN_LR
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#define PVR SPRN_PVR /* Processor Version */
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#define PIR SPRN_PIR /* Processor ID */
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#define PURR SPRN_PURR /* Processor Utilization of Resource Register */
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//#define RPA SPRN_RPA /* Required Physical Address Register */
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#define SDR1 SPRN_SDR1 /* MMU hash base register */
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#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
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#define SPR1 SPRN_SPRG1
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@ -389,10 +236,6 @@
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#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
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#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
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#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
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#define ICTC 1019
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#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
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#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
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#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
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#define XER SPRN_XER
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/* Processor Version Register (PVR) field extraction */
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