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[PATCH] sky2: driver update.
Here is revised patch against netdev sky2 branch. It includes whitespace fixes, all the changes from the previous review as well as some optimizations and timing fixes to solve some of the hangs. The stall problem is better but not perfect. It appears that under stress the chip can't keep up with the bus and sends a pause frame, then hangs. This version is for testing, and hopefully other eyes might see the root cause of the problem. I don't want to reinvent the ugly watchdog code in the syskonnect version of sk98lin. If you read it you will see, the original driver writer and the hardware developer obviously didn't understand each other. Dual port support is included, but not tested yet. It did require small change to NAPI since both ports share same IRQ. Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
d7f6884ae0
commit
793b883ed1
3 changed files with 817 additions and 630 deletions
1329
drivers/net/sky2.c
1329
drivers/net/sky2.c
File diff suppressed because it is too large
Load diff
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@ -209,13 +209,9 @@ enum csr_regs {
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Y2_CFG_SPC = 0x1c00,
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};
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/* Access pci config through board I/O */
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#define PCI_C(x) (Y2_CFG_SPC + (x))
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/* B0_CTST 16 bit Control/Status register */
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enum {
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Y2_VMAIN_AVAIL = 1<<17, /* VMAIN available (YUKON-2 only) */
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Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
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Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
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Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
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Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
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@ -234,13 +230,17 @@ enum {
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CS_MRST_SET = 1<<2, /* Set Master reset */
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CS_RST_CLR = 1<<1, /* Clear Software reset */
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CS_RST_SET = 1, /* Set Software reset */
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};
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/* B0_LED 8 Bit LED register */
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enum {
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/* Bit 7.. 2: reserved */
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LED_STAT_ON = 1<<1, /* Status LED on */
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LED_STAT_OFF = 1, /* Status LED off */
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LED_STAT_OFF = 1, /* Status LED off */
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};
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/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
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enum {
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PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
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PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
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PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
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@ -336,7 +336,7 @@ enum {
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Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
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Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
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Y2_HWE_ALL_MASK = Y2_IS_SENSOR | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
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Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
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Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |
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Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
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};
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@ -793,11 +793,6 @@ enum {
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STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
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STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
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STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
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ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
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ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
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ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
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ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
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};
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enum {
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@ -836,6 +831,7 @@ enum {
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/* WOL Pattern Counter Registers (YUKON only) */
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WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
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WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
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};
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@ -1536,34 +1532,34 @@ enum {
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/* Receive Frame Status Encoding */
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enum {
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GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
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GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
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GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
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GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
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GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
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GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
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GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
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GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
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GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
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GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
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GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
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GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
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GMR_FS_VLAN = 1<<13, /* VLAN Packet */
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GMR_FS_JABBER = 1<<12, /* Jabber Packet */
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GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
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GMR_FS_MC = 1<<10, /* Multicast Packet */
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GMR_FS_BC = 1<<9, /* Broadcast Packet */
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GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
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GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
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GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
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GMR_FS_MII_ERR = 1<<5, /* MII Error */
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GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
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GMR_FS_FRAGMENT = 1<<3, /* Fragment */
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GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
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GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
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GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
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GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
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/*
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* GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
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*/
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GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
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GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
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GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
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GMR_FS_UN_SIZE | GMR_FS_JABBER,
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/* Rx GMAC FIFO Flush Mask (default) */
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RX_FF_FL_DEF_MSK = GMR_FS_ANY_ERR,
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};
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/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
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enum {
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RX_TRUNC_ON = 1<<27, /* enable packet truncation */
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RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
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RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
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RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
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GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
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GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
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GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
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@ -1574,7 +1570,8 @@ enum {
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GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
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GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
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GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
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GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
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GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
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GMF_OPER_ON = 1<<3, /* Operational Mode On */
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GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
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GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
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@ -1586,6 +1583,9 @@ enum {
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/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
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enum {
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TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
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TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
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GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
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GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
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GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
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@ -1679,8 +1679,7 @@ enum {
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GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
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GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
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#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV |\
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GM_IS_TX_FF_UR | GM_IS_RX_FF_OR)
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#define GMAC_DEF_MSK (GM_IS_TX_FF_UR|GM_IS_RX_FF_OR)
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/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
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/* Bits 15.. 2: reserved */
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@ -1761,9 +1760,6 @@ enum {
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OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
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OP_RSS_HASH = 0x65,
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OP_TXINDEXLE = 0x68,
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/* YUKON-2 SPECIAL opcodes defines */
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OP_PUTIDX = 0x70,
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};
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/* Yukon 2 hardware interface
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@ -1775,62 +1771,60 @@ struct sky2_tx_le {
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struct {
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u16 offset;
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u16 start;
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} csum;
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} csum __attribute((packed));
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struct {
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u16 size;
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u16 rsvd;
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} tso;
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} tso __attribute((packed));
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} tx;
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u16 length; /* also vlan tag or checksum start */
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u8 ctrl;
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u8 opcode;
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};
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} __attribute((packed));
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struct sky2_rx_le {
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union {
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u32 addr;
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struct {
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u16 start1;
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u16 start2;
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} csum;
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} rx;
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u32 addr;
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u16 length;
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u8 ctrl;
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u8 opcode;
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};
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} __attribute((packed));;
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struct sky2_status_le {
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u32 status; /* also checksum */
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u16 length; /* also vlan tag */
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u8 link;
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u8 opcode;
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};
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} __attribute((packed));
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struct ring_info {
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struct sk_buff *skb;
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DECLARE_PCI_UNMAP_ADDR(mapaddr);
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DECLARE_PCI_UNMAP_LEN(maplen);
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dma_addr_t mapaddr;
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u16 maplen;
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u16 idx;
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};
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struct sky2_port {
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struct sky2_hw *hw ____cacheline_aligned;
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struct sky2_hw *hw;
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struct net_device *netdev;
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unsigned port;
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u32 msg_enable;
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struct ring_info *tx_ring ____cacheline_aligned;
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struct ring_info *tx_ring;
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struct sky2_tx_le *tx_le;
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spinlock_t tx_lock;
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u32 tx_addr64;
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u16 tx_cons; /* next le to check */
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u16 tx_prod; /* next le to use */
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u16 tx_pending;
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u16 tx_last_put;
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u16 tx_last_mss;
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struct ring_info *rx_ring ____cacheline_aligned;
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struct ring_info *rx_ring;
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struct sky2_rx_le *rx_le;
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u16 rx_ring_size;
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u32 rx_addr64;
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u16 rx_next; /* next re to check */
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u16 rx_put; /* next le index to use */
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u16 rx_pending;
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u16 rx_last_put;
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dma_addr_t rx_le_map;
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@ -1882,12 +1876,14 @@ static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
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return readb(hw->regs + reg);
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}
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/* This should probably go away, bus based tweeks suck */
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static inline int is_pciex(const struct sky2_hw *hw)
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{
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return (sky2_read32(hw, PCI_C(PCI_DEV_STATUS)) & PCI_OS_PCI_X) == 0;
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u32 status;
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pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
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return (status & PCI_OS_PCI_X) == 0;
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}
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static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
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{
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writel(val, hw->regs + reg);
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@ -780,11 +780,15 @@ static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits)
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}
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/* Schedule rx intr now? */
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static inline int netif_rx_schedule_test(struct net_device *dev)
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{
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return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
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}
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/* Schedule only if device is up */
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static inline int netif_rx_schedule_prep(struct net_device *dev)
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{
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return netif_running(dev) &&
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!test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
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return netif_running(dev) && netif_rx_schedule_test(dev);
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}
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/* Add interface to tail of rx poll list. This assumes that _prep has
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