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hwmon: (coretemp) Fix Atom CPUs support
Fix Atom CPUs support. Intel documents TjMax at 90 degrees C but some Atoms may have 125 degrees C (this is undocumented speculation). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Cc: Huaxu Wan <huaxu.wan@linux.intel.com> Cc: Kent Liu <kent.liu@linux.intel.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
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3 changed files with 23 additions and 14 deletions
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@ -4,7 +4,7 @@ Kernel driver coretemp
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Supported chips:
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* All Intel Core family
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Prefix: 'coretemp'
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CPUID: family 0x6, models 0xe, 0xf, 0x16, 0x17
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CPUID: family 0x6, models 0xe, 0xf, 0x16, 0x17, 0x1c (Atom)
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Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual
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Volume 3A: System Programming Guide
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http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
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@ -373,12 +373,12 @@ config SENSORS_GL520SM
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will be called gl520sm.
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config SENSORS_CORETEMP
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tristate "Intel Core (2) Duo/Solo temperature sensor"
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tristate "Intel Core/Core2/Atom temperature sensor"
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depends on X86 && EXPERIMENTAL
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help
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If you say yes here you get support for the temperature
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sensor inside your CPU. Supported all are all known variants
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of Intel Core family.
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sensor inside your CPU. Most of the family 6 CPUs
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are supported. Check documentation/driver for details.
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config SENSORS_IBMAEM
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tristate "IBM Active Energy Manager temperature/power sensors and control"
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@ -157,17 +157,24 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
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/* The 100C is default for both mobile and non mobile CPUs */
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int tjmax = 100000;
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int ismobile = 1;
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int usemsr_ee = 1;
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int err;
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u32 eax, edx;
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/* Early chips have no MSR for TjMax */
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if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
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ismobile = 0;
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usemsr_ee = 0;
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}
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if ((c->x86_model > 0xe) && (ismobile)) {
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/* Atoms seems to have TjMax at 90C */
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if (c->x86_model == 0x1c) {
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usemsr_ee = 0;
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tjmax = 90000;
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}
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if ((c->x86_model > 0xe) && (usemsr_ee)) {
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/* Now we can detect the mobile CPU using Intel provided table
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http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
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@ -179,13 +186,13 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
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dev_warn(dev,
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"Unable to access MSR 0x17, assuming desktop"
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" CPU\n");
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ismobile = 0;
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usemsr_ee = 0;
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} else if (!(eax & 0x10000000)) {
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ismobile = 0;
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usemsr_ee = 0;
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}
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}
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if (ismobile || c->x86_model == 0x1c) {
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if (usemsr_ee) {
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err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
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if (err) {
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@ -195,7 +202,9 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
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} else if (eax & 0x40000000) {
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tjmax = 85000;
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}
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} else {
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/* if we dont use msr EE it means we are desktop CPU (with exeception
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of Atom) */
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} else if (tjmax == 100000) {
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dev_warn(dev, "Using relative temperature scale!\n");
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}
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@ -248,9 +257,9 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, data);
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/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
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on older CPUs but not in this register */
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on older CPUs but not in this register, Atoms don't have it either */
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if (c->x86_model > 0xe) {
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if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
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err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
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if (err) {
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dev_warn(&pdev->dev, "Unable to read"
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@ -413,7 +422,7 @@ static int __init coretemp_init(void)
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for_each_online_cpu(i) {
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struct cpuinfo_x86 *c = &cpu_data(i);
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/* check if family 6, models 0xe, 0xf, 0x16, 0x17, 0x1A */
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/* check if family 6, models 0xe, 0xf, 0x16, 0x17, 0x1A, 0x1c */
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if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
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!((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
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(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
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