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[MIPS] Pb1550 code style cleanup
Fix a few errors and warnings given by checkpatch.pl: - macros with complex values not enclosed in parentheses; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - replace numeric literals with the matching macros; - properly indent the code and the array initializers; - insert spaces between operator and its operands, also remove excess spaces there; - remove space after the type cast's closing parenthesis; - insert missing space before closing brace in the array initializers; - replace spaces after the macro name with tabs in the #define directives, also sometimes insert space there for better looks; - remove excess tabs after the macro name in the #define directives; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Sergei Shtylyov
Ralf Baechle
parent
2091a17ff7
commit
6afabe6c93
5 changed files with 49 additions and 51 deletions
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@ -1,9 +1,8 @@
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#
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# Copyright 2000 MontaVista Software Inc.
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# Author: MontaVista Software, Inc.
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# ppopov@mvista.com or source@mvista.com
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# Copyright 2000, 2008 MontaVista Software Inc.
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# Author: MontaVista Software, Inc. <source@mvista.com>
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#
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# Makefile for the Alchemy Semiconductor PB1000 board.
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# Makefile for the Alchemy Semiconductor Pb1550 board.
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#
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lib-y := init.o board_setup.o irqmap.o
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@ -3,9 +3,8 @@
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* BRIEF MODULE DESCRIPTION
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* Alchemy Pb1550 board setup.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -35,15 +34,16 @@
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void board_reset(void)
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{
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/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
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au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C);
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/* Hit BCSR.SYSTEM[RESET] */
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au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
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}
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void __init board_setup(void)
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{
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u32 pin_func;
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/* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
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/*
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* Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
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* but it is board specific code, so put it here.
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*/
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pin_func = au_readl(SYS_PINFUNC);
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@ -51,8 +51,8 @@ void __init board_setup(void)
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pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
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au_writel(pin_func, SYS_PINFUNC);
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au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
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au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
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au_sync();
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printk("AMD Alchemy Pb1550 Board\n");
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printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
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}
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@ -1,11 +1,10 @@
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* PB1550 board setup
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* Pb1550 board setup
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -45,16 +44,15 @@ void __init prom_init(void)
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unsigned char *memsize_str;
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unsigned long memsize;
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prom_argc = (int) fw_arg0;
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prom_argv = (char **) fw_arg1;
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prom_envp = (char **) fw_arg2;
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prom_argc = (int)fw_arg0;
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prom_argv = (char **)fw_arg1;
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prom_envp = (char **)fw_arg2;
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prom_init_cmdline();
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memsize_str = prom_getenv("memsize");
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if (!memsize_str) {
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if (!memsize_str)
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memsize = 0x08000000;
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} else {
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memsize = simple_strtol(memsize_str, NULL, 0);
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}
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else
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memsize = strict_strtol(memsize_str, 0, NULL);
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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}
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@ -1,6 +1,6 @@
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/*
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* BRIEF MODULE DESCRIPTION
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* Au1xxx irq map table
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* Au1xx0 IRQ map table
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*
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* Copyright 2003 Embedded Edge, LLC
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* dan@embeddededge.com
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@ -31,8 +31,8 @@
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#include <asm/mach-au1x00/au1000.h>
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char irq_tab_alchemy[][5] __initdata = {
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[12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
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[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
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[12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
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[13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
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};
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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@ -30,15 +30,15 @@
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#include <linux/types.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define SMBUS_PSC_BASE PSC2_BASE_ADDR
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#define I2S_PSC_BASE PSC3_BASE_ADDR
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define SMBUS_PSC_BASE PSC2_BASE_ADDR
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#define I2S_PSC_BASE PSC3_BASE_ADDR
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#define BCSR_PHYS_ADDR 0xAF000000
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@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
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#define BCSR_SYSTEM_POWEROFF 0x4000
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#define BCSR_SYSTEM_RESET 0x8000
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
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/* VPP/VCC */
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#define SET_VCC_VPP(VCC, VPP, SLOT)\
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((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
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#define SET_VCC_VPP(VCC, VPP, SLOT) \
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((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
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#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
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#define PB1550_BOTH_BANKS
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@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
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#define PB1550_USER_ONLY
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#endif
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/* Timing values as described in databook, * ns value stripped of
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/*
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* Timing values as described in databook, * ns value stripped of
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* lower 2 bits.
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* These defines are here rather than an SOC1550 generic file because
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* the parts chosen on another board may be different and may require
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* different timings.
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*/
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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/* Bitfield shift amounts */
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#define NAND_T_H_SHIFT 0
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@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
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#define NAND_T_SU_SHIFT 8
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#define NAND_T_WH_SHIFT 12
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#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
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#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
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#define NAND_CS 1
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/* should be done by yamon */
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#define NAND_STCFG 0x00400005 /* 8-bit NAND */
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#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
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#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
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/* Should be done by YAMON */
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#define NAND_STCFG 0x00400005 /* 8-bit NAND */
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#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
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#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
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#endif /* __ASM_PB1550_H */
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