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drm/radeon/kms/avivo: fix some bugs in the display bandwidth setup
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
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2e7b6f7fa6
commit
69b3b5e59b
3 changed files with 28 additions and 5 deletions
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@ -38,6 +38,23 @@ typedef union rfixed {
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#define fixed_init_half(A) { .full = rfixed_const_half((A)) }
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#define rfixed_trunc(A) ((A).full >> 12)
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static inline u32 rfixed_floor(fixed20_12 A)
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{
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u32 non_frac = rfixed_trunc(A);
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return rfixed_const(non_frac);
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}
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static inline u32 rfixed_ceil(fixed20_12 A)
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{
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u32 non_frac = rfixed_trunc(A);
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if (A.full > rfixed_const(non_frac))
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return rfixed_const(non_frac + 1);
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else
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return rfixed_const(non_frac);
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}
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static inline u32 rfixed_div(fixed20_12 A, fixed20_12 B)
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{
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u64 tmp = ((u64)A.full << 13);
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@ -260,8 +260,9 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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b.full = rfixed_const(mode->crtc_hdisplay);
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c.full = rfixed_const(256);
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a.full = rfixed_mul(wm->num_line_pair, b);
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request_fifo_depth.full = rfixed_div(a, c);
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a.full = rfixed_div(b, c);
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request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
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request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
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if (a.full < rfixed_const(4)) {
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wm->lb_request_fifo_depth = 4;
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} else {
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@ -390,6 +391,7 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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a.full = rfixed_const(16);
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wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
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wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
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wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
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/* Determine estimated width */
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estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
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@ -399,6 +401,7 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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} else {
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a.full = rfixed_const(16);
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wm->priority_mark.full = rfixed_div(estimated_width, a);
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wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
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wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
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}
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}
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@ -889,8 +889,9 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
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b.full = rfixed_const(mode->crtc_hdisplay);
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c.full = rfixed_const(256);
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a.full = rfixed_mul(wm->num_line_pair, b);
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request_fifo_depth.full = rfixed_div(a, c);
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a.full = rfixed_div(b, c);
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request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
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request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
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if (a.full < rfixed_const(4)) {
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wm->lb_request_fifo_depth = 4;
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} else {
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@ -992,15 +993,17 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
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a.full = rfixed_const(16);
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wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
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wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
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wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
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/* Determine estimated width */
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estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
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estimated_width.full = rfixed_div(estimated_width, consumption_time);
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if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
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wm->priority_mark.full = rfixed_const(10);
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wm->priority_mark.full = wm->priority_mark_max.full;
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} else {
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a.full = rfixed_const(16);
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wm->priority_mark.full = rfixed_div(estimated_width, a);
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wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
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wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
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}
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}
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