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sh: intc - mark data structures as __initdata
With the intc core improved it is now possible to put the intc data structures in the initdata section. Version two of this patch puts the __initdata inside DECLARE_INTC_DESC() and removes the __initdata included in the board specific r2d code. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
46420e49c9
commit
5c37e02535
12 changed files with 79 additions and 82 deletions
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@ -71,9 +71,8 @@ static unsigned char irl2irq_r2d_1[R2D_NR_IRL] __initdata = {
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IRQ_TP,
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};
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static __initdata DECLARE_INTC_DESC(intc_desc_r2d_1, "r2d-1",
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vectors_r2d_1, NULL, NULL,
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mask_registers_r2d_1, NULL, NULL);
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static DECLARE_INTC_DESC(intc_desc_r2d_1, "r2d-1", vectors_r2d_1,
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NULL, NULL, mask_registers_r2d_1, NULL, NULL);
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#endif /* CONFIG_RTS7751R2D_1 */
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@ -110,9 +109,8 @@ static unsigned char irl2irq_r2d_plus[R2D_NR_IRL] __initdata = {
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IRQ_TP,
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};
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static __initdata DECLARE_INTC_DESC(intc_desc_r2d_plus, "r2d-plus",
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vectors_r2d_plus, NULL, NULL,
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mask_registers_r2d_plus, NULL, NULL);
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static DECLARE_INTC_DESC(intc_desc_r2d_plus, "r2d-plus", vectors_r2d_plus,
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NULL, NULL, mask_registers_r2d_plus, NULL, NULL);
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#endif /* CONFIG_RTS7751R2D_PLUS */
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@ -33,7 +33,7 @@ enum {
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UH, TWOD, ZD, PV, CI,
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};
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static struct intc_vect vectors[] = {
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(UP, IRQ_SM501_UP), INTC_IRQ(G54, IRQ_SM501_G54),
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INTC_IRQ(G53, IRQ_SM501_G53), INTC_IRQ(G52, IRQ_SM501_G52),
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INTC_IRQ(G51, IRQ_SM501_G51), INTC_IRQ(G50, IRQ_SM501_G50),
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@ -49,7 +49,7 @@ static struct intc_vect vectors[] = {
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INTC_IRQ(PV, IRQ_SM501_PV), INTC_IRQ(CI, IRQ_SM501_CI),
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};
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static struct intc_mask_reg mask_registers[] = {
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
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{ UP, G54, G53, G52, G51, G50, G49, G48,
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I2C, PW, 0, DMA, PCI, I2S, AC, US,
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@ -36,7 +36,7 @@ enum {
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RTC, TMU2, DMAC, USB, SCIF2, SCIF0,
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};
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static struct intc_vect vectors[] = {
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
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INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
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INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
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@ -57,7 +57,7 @@ static struct intc_vect vectors[] = {
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INTC_VECT(REF_RCMI, 0x580),
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};
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static struct intc_group groups[] = {
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
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INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
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@ -66,13 +66,13 @@ static struct intc_group groups[] = {
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INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
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};
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static struct intc_prio priorities[] = {
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static struct intc_prio priorities[] __initdata = {
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INTC_PRIO(DMAC, 7),
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INTC_PRIO(SCIF2, 3),
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INTC_PRIO(SCIF0, 3),
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};
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static struct intc_prio_reg prio_registers[] = {
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
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{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
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@ -87,7 +87,7 @@ static struct intc_prio_reg prio_registers[] = {
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static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups,
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priorities, NULL, prio_registers, NULL);
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static struct intc_vect vectors_irq[] = {
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static struct intc_vect vectors_irq[] __initdata = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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};
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@ -39,7 +39,7 @@ enum {
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RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
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};
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static struct intc_vect vectors[] = {
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
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INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
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@ -71,7 +71,7 @@ static struct intc_vect vectors[] = {
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#endif
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};
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static struct intc_group groups[] = {
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
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INTC_GROUP(REF, REF_RCMI, REF_ROVI),
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@ -81,14 +81,14 @@ static struct intc_group groups[] = {
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INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
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};
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static struct intc_prio priorities[] = {
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static struct intc_prio priorities[] __initdata = {
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INTC_PRIO(DMAC, 7),
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INTC_PRIO(SCI, 3),
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INTC_PRIO(SCIF2, 3),
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INTC_PRIO(SCIF0, 3),
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};
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static struct intc_prio_reg prio_registers[] = {
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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@ -114,7 +114,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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static struct intc_vect vectors_irq[] = {
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static struct intc_vect vectors_irq[] __initdata = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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};
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@ -37,7 +37,7 @@ enum {
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RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
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};
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static struct intc_vect vectors[] = {
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
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INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
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INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
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@ -63,7 +63,7 @@ static struct intc_vect vectors[] = {
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INTC_VECT(REF, 0x580),
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};
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static struct intc_group groups[] = {
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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@ -73,7 +73,7 @@ static struct intc_group groups[] = {
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INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
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};
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static struct intc_prio priorities[] = {
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static struct intc_prio priorities[] __initdata = {
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INTC_PRIO(DMAC1, 7),
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INTC_PRIO(DMAC2, 7),
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INTC_PRIO(SCIF0, 3),
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@ -85,7 +85,7 @@ static struct intc_prio priorities[] = {
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INTC_PRIO(EDMAC2, 5),
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};
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static struct intc_prio_reg prio_registers[] = {
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
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{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
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@ -103,7 +103,7 @@ static struct intc_prio_reg prio_registers[] = {
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static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
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priorities, NULL, prio_registers, NULL);
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static struct intc_vect vectors_irq[] = {
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static struct intc_vect vectors_irq[] __initdata = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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};
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@ -104,7 +104,7 @@ enum {
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DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
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};
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static struct intc_vect vectors[] = {
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
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@ -118,7 +118,7 @@ static struct intc_vect vectors[] = {
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INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
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};
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static struct intc_group groups[] = {
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
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@ -126,13 +126,13 @@ static struct intc_group groups[] = {
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INTC_GROUP(REF, REF_RCMI, REF_ROVI),
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};
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static struct intc_prio priorities[] = {
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static struct intc_prio priorities[] __initdata = {
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INTC_PRIO(SCIF, 3),
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INTC_PRIO(SCI1, 3),
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INTC_PRIO(DMAC, 7),
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};
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static struct intc_prio_reg prio_registers[] = {
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
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{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
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@ -150,13 +150,13 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7091)
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static struct intc_vect vectors_dma4[] = {
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static struct intc_vect vectors_dma4[] __initdata = {
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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INTC_VECT(DMAC_DMAE, 0x6c0),
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};
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static struct intc_group groups_dma4[] = {
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static struct intc_group groups_dma4[] __initdata = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMAE),
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};
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@ -168,7 +168,7 @@ static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
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/* SH7750R and SH7751R both have 8-channel DMA controllers */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_dma8[] = {
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static struct intc_vect vectors_dma8[] __initdata = {
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
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@ -176,7 +176,7 @@ static struct intc_vect vectors_dma8[] = {
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INTC_VECT(DMAC_DMAE, 0x6c0),
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};
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static struct intc_group groups_dma8[] = {
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static struct intc_group groups_dma8[] __initdata = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
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DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
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@ -191,11 +191,11 @@ static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_tmu34[] = {
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static struct intc_vect vectors_tmu34[] __initdata = {
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INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
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};
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static struct intc_mask_reg mask_registers[] = {
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, TMU4, TMU3,
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@ -210,7 +210,7 @@ static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
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#endif
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/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
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static struct intc_vect vectors_irlm[] = {
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static struct intc_vect vectors_irlm[] __initdata = {
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INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
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INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
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};
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@ -220,14 +220,14 @@ static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
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/* SH7751 and SH7751R both have PCI */
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#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_pci[] = {
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static struct intc_vect vectors_pci[] __initdata = {
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INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
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INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
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INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
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INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
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};
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static struct intc_group groups_pci[] = {
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static struct intc_group groups_pci[] __initdata = {
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INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
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};
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@ -43,7 +43,7 @@ enum {
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DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
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};
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static struct intc_vect vectors[] = {
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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@ -78,7 +78,7 @@ static struct intc_vect vectors[] = {
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INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
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};
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static struct intc_group groups[] = {
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
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DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
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@ -92,7 +92,7 @@ static struct intc_group groups[] = {
|
|||
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
|
||||
};
|
||||
|
||||
static struct intc_prio priorities[] = {
|
||||
static struct intc_prio priorities[] __initdata = {
|
||||
INTC_PRIO(SCIF0, 3),
|
||||
INTC_PRIO(SCIF1, 3),
|
||||
INTC_PRIO(SCIF2, 3),
|
||||
|
|
@ -101,7 +101,7 @@ static struct intc_prio priorities[] = {
|
|||
INTC_PRIO(DMABRG, 13),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] = {
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
|
||||
{ IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
|
||||
SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
|
||||
|
|
@ -117,7 +117,7 @@ static struct intc_mask_reg mask_registers[] = {
|
|||
0, MFI, 0, 0, 0, 0, ADC, CMT, } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] = {
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
|
||||
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
|
||||
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
|
||||
|
|
@ -134,7 +134,7 @@ static struct intc_prio_reg prio_registers[] = {
|
|||
static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
|
||||
priorities, mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct intc_vect vectors_irq[] = {
|
||||
static struct intc_vect vectors_irq[] __initdata = {
|
||||
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
|
||||
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ enum {
|
|||
SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] = {
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
|
||||
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
|
||||
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
|
||||
|
|
@ -117,7 +117,7 @@ static struct intc_vect vectors[] = {
|
|||
INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] = {
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
|
||||
|
|
@ -130,7 +130,7 @@ static struct intc_group groups[] = {
|
|||
INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
|
||||
};
|
||||
|
||||
static struct intc_prio priorities[] = {
|
||||
static struct intc_prio priorities[] __initdata = {
|
||||
INTC_PRIO(SCIF0, 3),
|
||||
INTC_PRIO(SCIF1, 3),
|
||||
INTC_PRIO(SCIF2, 3),
|
||||
|
|
@ -138,7 +138,7 @@ static struct intc_prio priorities[] = {
|
|||
INTC_PRIO(TMU1, 2),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] = {
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
|
||||
{ } },
|
||||
{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
|
||||
|
|
@ -168,7 +168,7 @@ static struct intc_mask_reg mask_registers[] = {
|
|||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] = {
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
|
||||
{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
|
||||
{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
|
||||
|
|
@ -185,7 +185,7 @@ static struct intc_prio_reg prio_registers[] = {
|
|||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_sense_reg sense_registers[] = {
|
||||
static struct intc_sense_reg sense_registers[] __initdata = {
|
||||
{ 0xa414001c, 16, 2, /* ICR1 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ enum {
|
|||
PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] = {
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
||||
INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(WDT, 0x560),
|
||||
|
|
@ -150,7 +150,7 @@ static struct intc_vect vectors[] = {
|
|||
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] = {
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
|
||||
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
|
||||
|
|
@ -167,12 +167,12 @@ static struct intc_group groups[] = {
|
|||
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
|
||||
};
|
||||
|
||||
static struct intc_prio priorities[] = {
|
||||
static struct intc_prio priorities[] __initdata = {
|
||||
INTC_PRIO(SCIF0, 3),
|
||||
INTC_PRIO(SCIF1, 3),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] = {
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
|
||||
{ 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
|
||||
SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
|
||||
|
|
@ -180,7 +180,7 @@ static struct intc_mask_reg mask_registers[] = {
|
|||
HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] = {
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
|
||||
TMU2, TMU2_TICPI } },
|
||||
{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
|
||||
|
|
@ -199,24 +199,24 @@ static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
|
|||
|
||||
/* Support for external interrupt pins in IRQ mode */
|
||||
|
||||
static struct intc_vect irq_vectors[] = {
|
||||
static struct intc_vect irq_vectors[] __initdata = {
|
||||
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
|
||||
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
|
||||
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
|
||||
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg irq_mask_registers[] = {
|
||||
static struct intc_mask_reg irq_mask_registers[] __initdata = {
|
||||
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg irq_prio_registers[] = {
|
||||
static struct intc_prio_reg irq_prio_registers[] __initdata = {
|
||||
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_sense_reg irq_sense_registers[] = {
|
||||
static struct intc_sense_reg irq_sense_registers[] __initdata = {
|
||||
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
|
@ -227,7 +227,7 @@ static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
|
|||
|
||||
/* External interrupt pins in IRL mode */
|
||||
|
||||
static struct intc_vect irl_vectors[] = {
|
||||
static struct intc_vect irl_vectors[] __initdata = {
|
||||
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
|
||||
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
|
||||
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
|
||||
|
|
@ -238,7 +238,7 @@ static struct intc_vect irl_vectors[] = {
|
|||
INTC_VECT(IRL_HHHL, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg irl3210_mask_registers[] = {
|
||||
static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
|
||||
{ 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
|
||||
{ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
|
||||
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
|
||||
|
|
@ -246,7 +246,7 @@ static struct intc_mask_reg irl3210_mask_registers[] = {
|
|||
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg irl7654_mask_registers[] = {
|
||||
static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
|
||||
{ 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@ enum {
|
|||
PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] = {
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(WDT, 0x560),
|
||||
INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
|
||||
INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
|
||||
|
|
@ -158,7 +158,7 @@ static struct intc_vect vectors[] = {
|
|||
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] = {
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
|
||||
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
|
||||
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
|
||||
|
|
@ -175,7 +175,7 @@ static struct intc_group groups[] = {
|
|||
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
|
||||
};
|
||||
|
||||
static struct intc_prio priorities[] = {
|
||||
static struct intc_prio priorities[] __initdata = {
|
||||
INTC_PRIO(SCIF0, 3),
|
||||
INTC_PRIO(SCIF1, 3),
|
||||
INTC_PRIO(SCIF2, 3),
|
||||
|
|
@ -184,7 +184,7 @@ static struct intc_prio priorities[] = {
|
|||
INTC_PRIO(SCIF5, 3),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] = {
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
|
||||
|
|
@ -205,7 +205,7 @@ static struct intc_mask_reg mask_registers[] = {
|
|||
SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] = {
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
|
||||
|
|
@ -227,20 +227,19 @@ static struct intc_prio_reg prio_registers[] = {
|
|||
static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
|
||||
/* Support for external interrupt pins in IRQ mode */
|
||||
|
||||
static struct intc_vect vectors_irq0123[] = {
|
||||
static struct intc_vect vectors_irq0123[] __initdata = {
|
||||
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
|
||||
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irq4567[] = {
|
||||
static struct intc_vect vectors_irq4567[] __initdata = {
|
||||
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
|
||||
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
|
||||
};
|
||||
|
||||
static struct intc_sense_reg sense_registers[] = {
|
||||
static struct intc_sense_reg sense_registers[] __initdata = {
|
||||
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
|
@ -255,7 +254,7 @@ static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
|
|||
|
||||
/* External interrupt pins in IRL mode */
|
||||
|
||||
static struct intc_vect vectors_irl0123[] = {
|
||||
static struct intc_vect vectors_irl0123[] __initdata = {
|
||||
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
|
||||
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
|
||||
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
|
||||
|
|
@ -266,7 +265,7 @@ static struct intc_vect vectors_irl0123[] = {
|
|||
INTC_VECT(IRL0_HHHL, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irl4567[] = {
|
||||
static struct intc_vect vectors_irl4567[] __initdata = {
|
||||
INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
|
||||
INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
|
||||
INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ enum {
|
|||
DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] = {
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(HUDII, 0x3e0),
|
||||
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
||||
INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
|
||||
|
|
@ -145,7 +145,7 @@ static struct intc_vect vectors[] = {
|
|||
INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] = {
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
|
||||
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
|
||||
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
|
||||
|
|
@ -165,14 +165,14 @@ static struct intc_group groups[] = {
|
|||
INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
|
||||
};
|
||||
|
||||
static struct intc_prio priorities[] = {
|
||||
static struct intc_prio priorities[] __initdata = {
|
||||
INTC_PRIO(SCIF0, 3),
|
||||
INTC_PRIO(SCIF1, 3),
|
||||
INTC_PRIO(SCIF2, 3),
|
||||
INTC_PRIO(SCIF3, 3),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] = {
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
|
||||
|
|
@ -197,7 +197,7 @@ static struct intc_mask_reg mask_registers[] = {
|
|||
SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] = {
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
|
||||
{ 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
|
||||
|
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@ -222,12 +222,12 @@ static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
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mask_registers, prio_registers, NULL);
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/* Support for external interrupt pins in IRQ mode */
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static struct intc_vect vectors_irq[] = {
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static struct intc_vect vectors_irq[] __initdata = {
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INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
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INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
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||||
};
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static struct intc_sense_reg sense_registers[] = {
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static struct intc_sense_reg sense_registers[] __initdata = {
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{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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};
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@ -236,7 +236,7 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
|
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sense_registers);
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||||
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/* External interrupt pins in IRL mode */
|
||||
static struct intc_vect vectors_irl[] = {
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||||
static struct intc_vect vectors_irl[] __initdata = {
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||||
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
|
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INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
|
||||
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
|
||||
|
|
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|||
|
|
@ -42,10 +42,10 @@ struct intc_prio {
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|||
|
||||
struct intc_group {
|
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intc_enum enum_id;
|
||||
intc_enum *enum_ids;
|
||||
intc_enum enum_ids[32];
|
||||
};
|
||||
|
||||
#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
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#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
|
||||
|
||||
struct intc_mask_reg {
|
||||
unsigned long set_reg, clr_reg, reg_width;
|
||||
|
|
@ -81,7 +81,7 @@ struct intc_desc {
|
|||
#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
|
||||
#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
|
||||
priorities, mask_regs, prio_regs, sense_regs) \
|
||||
struct intc_desc symbol = { \
|
||||
struct intc_desc symbol __initdata = { \
|
||||
_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
|
||||
_INTC_ARRAY(priorities), \
|
||||
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
|
||||
|
|
|
|||
Loading…
Reference in a new issue