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Attack of "the the"s in arch

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The patch below corrects multiple occurances of "the the"
typos across several files, both in source comments and KConfig files.
There is no actual code changed, only text.  Note this only affects the /arch
directory, and I believe I could find many more elsewhere. :)

Signed-off-by: Adrian Bunk <bunk@stusta.de>
This commit is contained in:
Matt LaPlante 2006-10-03 22:21:02 +02:00 committed by Adrian Bunk
parent bf6ee0ae49
commit 4b3f686d4a
14 changed files with 18 additions and 18 deletions
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2
arch/arm/mach-lh7a40x/arch-lpd7a40x.c
View file

@ -164,7 +164,7 @@ static void lh7a40x_ack_cpld_irq (u32 irq)
/* CPLD doesn't have ack capability, but some devices may */
#if defined (CPLD_INTMASK_TOUCH)
/* The touch control *must* mask the the interrupt because the
/* The touch control *must* mask the interrupt because the
* interrupt bit is read by the driver to determine if the pen
* is still down. */
if (irq == IRQ_TOUCH)

2
arch/i386/Kconfig
View file

@ -682,7 +682,7 @@ config EFI
depends on ACPI
default n
---help---
This enables the the kernel to boot on EFI platforms using
This enables the kernel to boot on EFI platforms using
system configuration information passed to it from the firmware.
This also enables the kernel to use any EFI runtime services that are
available (such as the EFI variable services).

2
arch/i386/pci/fixup.c
View file

@ -393,7 +393,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
* We pretend to bring them out of full D3 state, and restore the proper
* IRQ, PCI cache line size, and BARs, otherwise the device won't function
* properly. In some cases, the device will generate an interrupt on
* the wrong IRQ line, causing any devices sharing the the line it's
* the wrong IRQ line, causing any devices sharing the line it's
* *supposed* to use to be disabled by the kernel's IRQ debug code.
*/
static u16 toshiba_line_size;

2
arch/ia64/sn/kernel/xpnet.c
View file

@ -225,7 +225,7 @@ xpnet_receive(partid_t partid, int channel, struct xpnet_message *msg)
skb_put(skb, (msg->size - msg->leadin_ignore - msg->tailout_ignore));
/*
* Move the data over from the the other side.
* Move the data over from the other side.
*/
if ((XPNET_VERSION_MINOR(msg->version) == 1) &&
(msg->embedded_bytes != 0)) {

2
arch/m68knommu/Kconfig
View file

@ -495,7 +495,7 @@ config VECTORBASE
hex "Address of the base of system vectors"
default "0"
help
Define the address of the the system vectors. Commonly this is
Define the address of the system vectors. Commonly this is
put at the start of RAM, but it doesn't have to be. On ColdFire
platforms this address is programmed into the VBR register, thus
actually setting the address to use.

2
arch/mips/mm/tlbex.c
View file

@ -1211,7 +1211,7 @@ static void __init build_r4000_tlb_refill_handler(void)
* Overflow check: For the 64bit handler, we need at least one
* free instruction slot for the wrap-around branch. In worst
* case, if the intended insertion point is a delay slot, we
* need three, with the the second nop'ed and the third being
* need three, with the second nop'ed and the third being
* unused.
*/
#ifdef CONFIG_32BIT

4
arch/parisc/kernel/entry.S
View file

@ -941,8 +941,8 @@ syscall_exit_rfi:
* to "proper" values now (otherwise we'll wind up restoring
* whatever was last stored in the task structure, which might
* be inconsistent if an interrupt occured while on the gateway
* page) Note that we may be "trashing" values the user put in
* them, but we don't support the the user changing them.
* page). Note that we may be "trashing" values the user put in
* them, but we don't support the user changing them.
*/
STREG %r0,PT_SR2(%r16)

4
arch/powerpc/Kconfig
View file

@ -1002,7 +1002,7 @@ config CONSISTENT_START_BOOL
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
help
This option allows you to set the base virtual address
of the the consistent memory pool. This pool of virtual
of the consistent memory pool. This pool of virtual
memory is used to make consistent memory allocations.
config CONSISTENT_START
@ -1013,7 +1013,7 @@ config CONSISTENT_SIZE_BOOL
bool "Set custom consistent memory pool size"
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
help
This option allows you to set the size of the the
This option allows you to set the size of the
consistent memory pool. This pool of virtual memory
is used to make consistent memory allocations.

4
arch/ppc/Kconfig
View file

@ -1345,7 +1345,7 @@ config CONSISTENT_START_BOOL
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
help
This option allows you to set the base virtual address
of the the consistent memory pool. This pool of virtual
of the consistent memory pool. This pool of virtual
memory is used to make consistent memory allocations.
config CONSISTENT_START
@ -1356,7 +1356,7 @@ config CONSISTENT_SIZE_BOOL
bool "Set custom consistent memory pool size"
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
help
This option allows you to set the size of the the
This option allows you to set the size of the
consistent memory pool. This pool of virtual memory
is used to make consistent memory allocations.

2
arch/um/Makefile
View file

@ -102,7 +102,7 @@ linux: vmlinux
define archhelp
echo '* linux - Binary kernel image (./linux) - for backward'
echo ' compatibility only, this creates a hard link to the'
echo ' real kernel binary, the the "vmlinux" binary you'
echo ' real kernel binary, the "vmlinux" binary you'
echo ' find in the kernel root.'
endef

2
arch/um/drivers/line.c
View file

@ -497,7 +497,7 @@ void close_lines(struct line *lines, int nlines)
}
/* Common setup code for both startup command line and mconsole initialization.
* @lines contains the the array (of size @num) to modify;
* @lines contains the array (of size @num) to modify;
* @init is the setup string;
*/

2
arch/um/include/sysdep-x86_64/ptrace_user.h
View file

@ -55,7 +55,7 @@
#define PTRACE_OLDSETOPTIONS 21
#endif
/* These are before the system call, so the the system call number is RAX
/* These are before the system call, so the system call number is RAX
* rather than ORIG_RAX, and arg4 is R10 rather than RCX
*/
#define REGS_SYSCALL_NR PT_INDEX(RAX)

2
arch/v850/kernel/entry.S
View file

@ -195,7 +195,7 @@
sst.w lp, PTO+PT_GPR(GPR_LP)[ep]; \
type ## _STATE_SAVER
/* Pop a register state pushed by PUSH_STATE, except for the stack pointer,
from the the stack. */
from the stack. */
#define POP_STATE(type) \
mov sp, ep; \
type ## _STATE_RESTORER; \

4
arch/xtensa/lib/usercopy.S
View file

@ -5,10 +5,10 @@
*
* DO NOT COMBINE this function with <arch/xtensa/lib/hal/memcopy.S>.
* It needs to remain separate and distinct. The hal files are part
* of the the Xtensa link-time HAL, and those files may differ per
* of the Xtensa link-time HAL, and those files may differ per
* processor configuration. Patching the kernel for another
* processor configuration includes replacing the hal files, and we
* could loose the special functionality for accessing user-space
* could lose the special functionality for accessing user-space
* memory during such a patch. We sacrifice a little code space here
* in favor to simplify code maintenance.
*