mirror of
https://github.com/adulau/aha.git
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gru: update irq infrastructure
Update the GRU irq allocate/free functions to use the latest upstream infrastructure. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Jack Steiner
Linus Torvalds
parent
67bf04a5c2
commit
4107e1d38a
4 changed files with 260 additions and 70 deletions
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@ -133,19 +133,6 @@ static void gru_cb_set_istatus_active(struct gru_instruction_bits *cbk)
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}
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}
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/*
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* Convert a interrupt IRQ to a pointer to the GRU GTS that caused the
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* interrupt. Interrupts are always sent to a cpu on the blade that contains the
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* GRU (except for headless blades which are not currently supported). A blade
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* has N grus; a block of N consecutive IRQs is assigned to the GRUs. The IRQ
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* number uniquely identifies the GRU chiplet on the local blade that caused the
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* interrupt. Always called in interrupt context.
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*/
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static inline struct gru_state *irq_to_gru(int irq)
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{
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return &gru_base[uv_numa_blade_id()]->bs_grus[irq - IRQ_GRU];
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}
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/*
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* Read & clear a TFM
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*
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@ -449,7 +436,7 @@ failactive:
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* Note that this is the interrupt handler that is registered with linux
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* interrupt handlers.
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*/
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irqreturn_t gru_intr(int irq, void *dev_id)
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static irqreturn_t gru_intr(int chiplet, int blade)
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{
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struct gru_state *gru;
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struct gru_tlb_fault_map imap, dmap;
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@ -459,13 +446,18 @@ irqreturn_t gru_intr(int irq, void *dev_id)
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STAT(intr);
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gru = irq_to_gru(irq);
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gru = &gru_base[blade]->bs_grus[chiplet];
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if (!gru) {
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dev_err(grudev, "GRU: invalid interrupt: cpu %d, irq %d\n",
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raw_smp_processor_id(), irq);
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dev_err(grudev, "GRU: invalid interrupt: cpu %d, chiplet %d\n",
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raw_smp_processor_id(), chiplet);
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return IRQ_NONE;
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}
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get_clear_fault_map(gru, &imap, &dmap);
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gru_dbg(grudev,
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"cpu %d, chiplet %d, gid %d, imap %016lx %016lx, dmap %016lx %016lx\n",
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smp_processor_id(), chiplet, gru->gs_gid,
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imap.fault_bits[0], imap.fault_bits[1],
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dmap.fault_bits[0], dmap.fault_bits[1]);
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for_each_cbr_in_tfm(cbrnum, dmap.fault_bits) {
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complete(gru->gs_blade->bs_async_wq);
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@ -503,6 +495,29 @@ irqreturn_t gru_intr(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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irqreturn_t gru0_intr(int irq, void *dev_id)
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{
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return gru_intr(0, uv_numa_blade_id());
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}
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irqreturn_t gru1_intr(int irq, void *dev_id)
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{
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return gru_intr(1, uv_numa_blade_id());
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}
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irqreturn_t gru_intr_mblade(int irq, void *dev_id)
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{
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int blade;
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for_each_possible_blade(blade) {
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if (uv_blade_nr_possible_cpus(blade))
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continue;
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gru_intr(0, blade);
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gru_intr(1, blade);
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}
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return IRQ_HANDLED;
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}
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static int gru_user_dropin(struct gru_thread_state *gts,
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struct gru_tlb_fault_handle *tfh,
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@ -35,6 +35,9 @@
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#include <linux/interrupt.h>
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#include <linux/proc_fs.h>
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#include <linux/uaccess.h>
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#ifdef CONFIG_X86_64
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#include <asm/uv/uv_irq.h>
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#endif
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#include <asm/uv/uv.h>
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#include "gru.h"
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#include "grulib.h"
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@ -130,7 +133,6 @@ static int gru_create_new_context(unsigned long arg)
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struct gru_vma_data *vdata;
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int ret = -EINVAL;
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if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
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return -EFAULT;
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@ -302,34 +304,210 @@ fail:
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return -ENOMEM;
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}
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static void gru_free_tables(void)
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{
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int bid;
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int order = get_order(sizeof(struct gru_state) *
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GRU_CHIPLETS_PER_BLADE);
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for (bid = 0; bid < GRU_MAX_BLADES; bid++)
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free_pages((unsigned long)gru_base[bid], order);
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}
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static unsigned long gru_chiplet_cpu_to_mmr(int chiplet, int cpu, int *corep)
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{
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unsigned long mmr = 0;
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int core;
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/*
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* We target the cores of a blade and not the hyperthreads themselves.
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* There is a max of 8 cores per socket and 2 sockets per blade,
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* making for a max total of 16 cores (i.e., 16 CPUs without
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* hyperthreading and 32 CPUs with hyperthreading).
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*/
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core = uv_cpu_core_number(cpu) + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
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if (core >= GRU_NUM_TFM || uv_cpu_ht_number(cpu))
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return 0;
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if (chiplet == 0) {
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mmr = UVH_GR0_TLB_INT0_CONFIG +
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core * (UVH_GR0_TLB_INT1_CONFIG - UVH_GR0_TLB_INT0_CONFIG);
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} else if (chiplet == 1) {
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mmr = UVH_GR1_TLB_INT0_CONFIG +
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core * (UVH_GR1_TLB_INT1_CONFIG - UVH_GR1_TLB_INT0_CONFIG);
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} else {
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BUG();
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}
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*corep = core;
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return mmr;
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}
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#ifdef CONFIG_IA64
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static int get_base_irq(void)
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static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];
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static void gru_noop(unsigned int irq)
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{
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return IRQ_GRU;
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}
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static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
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[0 ... GRU_CHIPLETS_PER_BLADE - 1] {
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.mask = gru_noop,
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.unmask = gru_noop,
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.ack = gru_noop
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}
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};
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static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
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irq_handler_t irq_handler, int cpu, int blade)
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{
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unsigned long mmr;
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int irq = IRQ_GRU + chiplet;
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int ret, core;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr == 0)
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return 0;
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if (gru_irq_count[chiplet] == 0) {
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gru_chip[chiplet].name = irq_name;
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ret = set_irq_chip(irq, &gru_chip[chiplet]);
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if (ret) {
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printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -ret);
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return ret;
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}
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ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
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if (ret) {
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printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -ret);
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return ret;
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}
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}
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gru_irq_count[chiplet]++;
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return 0;
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}
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static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
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{
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unsigned long mmr;
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int core, irq = IRQ_GRU + chiplet;
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if (gru_irq_count[chiplet] == 0)
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return;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr == 0)
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return;
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if (--gru_irq_count[chiplet] == 0)
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free_irq(irq, NULL);
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}
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#elif defined CONFIG_X86_64
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static void noop(unsigned int irq)
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static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
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irq_handler_t irq_handler, int cpu, int blade)
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{
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unsigned long mmr;
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int irq, core;
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int ret;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr == 0)
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return 0;
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irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
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if (irq < 0) {
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printk(KERN_ERR "%s: uv_setup_irq failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -irq);
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return irq;
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}
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ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
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if (ret) {
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uv_teardown_irq(irq);
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printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -ret);
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return ret;
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}
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gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
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return 0;
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}
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static struct irq_chip gru_chip = {
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.name = "gru",
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.mask = noop,
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.unmask = noop,
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.ack = noop,
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};
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static int get_base_irq(void)
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static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
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{
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set_irq_chip(IRQ_GRU, &gru_chip);
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set_irq_chip(IRQ_GRU + 1, &gru_chip);
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return IRQ_GRU;
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int irq, core;
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unsigned long mmr;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr) {
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irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
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if (irq) {
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free_irq(irq, NULL);
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uv_teardown_irq(irq);
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}
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}
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}
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#endif
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static void gru_teardown_tlb_irqs(void)
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{
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int blade;
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int cpu;
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for_each_online_cpu(cpu) {
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blade = uv_cpu_to_blade_id(cpu);
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gru_chiplet_teardown_tlb_irq(0, cpu, blade);
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gru_chiplet_teardown_tlb_irq(1, cpu, blade);
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}
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for_each_possible_blade(blade) {
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if (uv_blade_nr_possible_cpus(blade))
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continue;
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gru_chiplet_teardown_tlb_irq(0, 0, blade);
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gru_chiplet_teardown_tlb_irq(1, 0, blade);
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}
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}
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static int gru_setup_tlb_irqs(void)
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{
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int blade;
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int cpu;
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int ret;
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for_each_online_cpu(cpu) {
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blade = uv_cpu_to_blade_id(cpu);
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ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
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if (ret != 0)
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goto exit1;
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ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
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if (ret != 0)
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goto exit1;
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}
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for_each_possible_blade(blade) {
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if (uv_blade_nr_possible_cpus(blade))
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continue;
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ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
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if (ret != 0)
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goto exit1;
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ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);
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if (ret != 0)
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goto exit1;
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}
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return 0;
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exit1:
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gru_teardown_tlb_irqs();
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return ret;
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}
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/*
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* gru_init
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*
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@ -337,8 +515,7 @@ static int get_base_irq(void)
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*/
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static int __init gru_init(void)
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{
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int ret, irq, chip;
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char id[10];
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int ret;
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if (!is_uv_system())
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return 0;
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@ -353,41 +530,29 @@ static int __init gru_init(void)
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gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
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printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
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gru_start_paddr, gru_end_paddr);
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irq = get_base_irq();
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for (chip = 0; chip < GRU_CHIPLETS_PER_BLADE; chip++) {
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ret = request_irq(irq + chip, gru_intr, 0, id, NULL);
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/* TODO: fix irq handling on x86. For now ignore failure because
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* interrupts are not required & not yet fully supported */
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if (ret) {
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printk(KERN_WARNING
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"!!!WARNING: GRU ignoring request failure!!!\n");
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ret = 0;
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}
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if (ret) {
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printk(KERN_ERR "%s: request_irq failed\n",
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GRU_DRIVER_ID_STR);
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goto exit1;
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}
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}
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ret = misc_register(&gru_miscdev);
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if (ret) {
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printk(KERN_ERR "%s: misc_register failed\n",
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GRU_DRIVER_ID_STR);
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goto exit1;
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goto exit0;
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}
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ret = gru_proc_init();
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if (ret) {
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printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
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goto exit2;
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goto exit1;
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}
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ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
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if (ret) {
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printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
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goto exit3;
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goto exit2;
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}
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ret = gru_setup_tlb_irqs();
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if (ret != 0)
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goto exit3;
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gru_kservices_init();
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printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
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@ -395,31 +560,24 @@ static int __init gru_init(void)
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return 0;
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exit3:
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gru_proc_exit();
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gru_free_tables();
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exit2:
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misc_deregister(&gru_miscdev);
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gru_proc_exit();
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exit1:
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for (--chip; chip >= 0; chip--)
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free_irq(irq + chip, NULL);
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misc_deregister(&gru_miscdev);
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exit0:
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return ret;
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}
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static void __exit gru_exit(void)
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{
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int i, bid;
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int order = get_order(sizeof(struct gru_state) *
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GRU_CHIPLETS_PER_BLADE);
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if (!is_uv_system())
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return;
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for (i = 0; i < GRU_CHIPLETS_PER_BLADE; i++)
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free_irq(IRQ_GRU + i, NULL);
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gru_teardown_tlb_irqs();
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gru_kservices_exit();
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for (bid = 0; bid < GRU_MAX_BLADES; bid++)
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free_pages((unsigned long)gru_base[bid], order);
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gru_free_tables();
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misc_deregister(&gru_miscdev);
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gru_proc_exit();
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}
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@ -49,12 +49,16 @@ struct device *grudev = &gru_device;
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/*
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* Select a gru fault map to be used by the current cpu. Note that
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* multiple cpus may be using the same map.
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* ZZZ should "shift" be used?? Depends on HT cpu numbering
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* ZZZ should be inline but did not work on emulator
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*/
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int gru_cpu_fault_map_id(void)
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{
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return uv_blade_processor_id() % GRU_NUM_TFM;
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int cpu = smp_processor_id();
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int id, core;
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core = uv_cpu_core_number(cpu);
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id = core + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
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return id;
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}
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/*--------- ASID Management -------------------------------------------
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@ -605,6 +609,7 @@ void gru_load_context(struct gru_thread_state *gts)
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cch->unmap_enable = 1;
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cch->tfm_done_bit_enable = 1;
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cch->cb_int_enable = 1;
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cch->tlb_int_select = 0; /* For now, ints go to cpu 0 */
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} else {
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cch->unmap_enable = 0;
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cch->tfm_done_bit_enable = 0;
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@ -444,6 +444,7 @@ struct gru_state {
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in use */
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struct gru_thread_state *gs_gts[GRU_NUM_CCH]; /* GTS currently using
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the context */
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int gs_irq[GRU_NUM_TFM]; /* Interrupt irqs */
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};
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/*
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||||
|
|
@ -610,6 +611,15 @@ static inline int is_kernel_context(struct gru_thread_state *gts)
|
|||
return !gts->ts_mm;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following are for Nehelem-EX. A more general scheme is needed for
|
||||
* future processors.
|
||||
*/
|
||||
#define UV_MAX_INT_CORES 8
|
||||
#define uv_cpu_socket_number(p) ((cpu_physical_id(p) >> 5) & 1)
|
||||
#define uv_cpu_ht_number(p) (cpu_physical_id(p) & 1)
|
||||
#define uv_cpu_core_number(p) (((cpu_physical_id(p) >> 2) & 4) | \
|
||||
((cpu_physical_id(p) >> 1) & 3))
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function prototypes & externs
|
||||
*/
|
||||
|
|
@ -633,9 +643,11 @@ extern void gts_drop(struct gru_thread_state *gts);
|
|||
extern void gru_tgh_flush_init(struct gru_state *gru);
|
||||
extern int gru_kservices_init(void);
|
||||
extern void gru_kservices_exit(void);
|
||||
extern irqreturn_t gru0_intr(int irq, void *dev_id);
|
||||
extern irqreturn_t gru1_intr(int irq, void *dev_id);
|
||||
extern irqreturn_t gru_intr_mblade(int irq, void *dev_id);
|
||||
extern int gru_dump_chiplet_request(unsigned long arg);
|
||||
extern long gru_get_gseg_statistics(unsigned long arg);
|
||||
extern irqreturn_t gru_intr(int irq, void *dev_id);
|
||||
extern int gru_handle_user_call_os(unsigned long address);
|
||||
extern int gru_user_flush_tlb(unsigned long arg);
|
||||
extern int gru_user_unload_context(unsigned long arg);
|
||||
|
|
|
|||
Loading…
Reference in a new issue