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pcnet32: endianness
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Al Viro
David S. Miller
parent
03a710ffcb
commit
3e33545ba6
1 changed files with 48 additions and 50 deletions
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@ -210,31 +210,31 @@ static int homepna[MAX_UNITS];
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/* The PCNET32 Rx and Tx ring descriptors. */
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struct pcnet32_rx_head {
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u32 base;
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s16 buf_length; /* two`s complement of length */
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s16 status;
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u32 msg_length;
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u32 reserved;
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__le32 base;
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__le16 buf_length; /* two`s complement of length */
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__le16 status;
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__le32 msg_length;
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__le32 reserved;
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};
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struct pcnet32_tx_head {
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u32 base;
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s16 length; /* two`s complement of length */
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s16 status;
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u32 misc;
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u32 reserved;
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__le32 base;
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__le16 length; /* two`s complement of length */
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__le16 status;
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__le32 misc;
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__le32 reserved;
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};
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/* The PCNET32 32-Bit initialization block, described in databook. */
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struct pcnet32_init_block {
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u16 mode;
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u16 tlen_rlen;
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__le16 mode;
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__le16 tlen_rlen;
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u8 phys_addr[6];
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u16 reserved;
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u32 filter[2];
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__le16 reserved;
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__le32 filter[2];
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/* Receive and transmit ring base, along with extra bits. */
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u32 rx_ring;
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u32 tx_ring;
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__le32 rx_ring;
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__le32 tx_ring;
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};
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/* PCnet32 access functions */
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@ -610,9 +610,9 @@ static void pcnet32_realloc_rx_ring(struct net_device *dev,
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new_dma_addr_list[new] =
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pci_map_single(lp->pci_dev, rx_skbuff->data,
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PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
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new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
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new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
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new_rx_ring[new].status = le16_to_cpu(0x8000);
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new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
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new_rx_ring[new].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
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new_rx_ring[new].status = cpu_to_le16(0x8000);
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}
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/* and free any unneeded buffers */
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for (; new < lp->rx_ring_size; new++) {
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@ -888,7 +888,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
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int x, i; /* counters */
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int numbuffs = 4; /* number of TX/RX buffers and descs */
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u16 status = 0x8300; /* TX ring status */
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u16 teststatus; /* test of ring status */
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__le16 teststatus; /* test of ring status */
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int rc; /* return code */
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int size; /* size of packets */
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unsigned char *packet; /* source packet data */
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@ -935,7 +935,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
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packet = skb->data;
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skb_put(skb, size); /* create space for data */
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lp->tx_skbuff[x] = skb;
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lp->tx_ring[x].length = le16_to_cpu(-skb->len);
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lp->tx_ring[x].length = cpu_to_le16(-skb->len);
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lp->tx_ring[x].misc = 0;
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/* put DA and SA into the skb */
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@ -955,10 +955,9 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
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lp->tx_dma_addr[x] =
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pci_map_single(lp->pci_dev, skb->data, skb->len,
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PCI_DMA_TODEVICE);
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lp->tx_ring[x].base =
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(u32) le32_to_cpu(lp->tx_dma_addr[x]);
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lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
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wmb(); /* Make sure owner changes after all others are visible */
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lp->tx_ring[x].status = le16_to_cpu(status);
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lp->tx_ring[x].status = cpu_to_le16(status);
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}
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}
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@ -969,7 +968,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
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x = a->read_csr(ioaddr, CSR15) & 0xfffc;
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lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
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teststatus = le16_to_cpu(0x8000);
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teststatus = cpu_to_le16(0x8000);
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lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
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/* Check status of descriptors */
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@ -1099,6 +1098,7 @@ static int pcnet32_phys_id(struct net_device *dev, u32 data)
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mod_timer(&lp->blink_timer, jiffies);
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set_current_state(TASK_INTERRUPTIBLE);
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/* AV: the limit here makes no sense whatsoever */
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if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
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data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
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@ -1224,7 +1224,7 @@ static void pcnet32_rx_entry(struct net_device *dev,
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newskb->data,
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PKT_BUF_SZ - 2,
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PCI_DMA_FROMDEVICE);
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rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
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rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
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rx_in_place = 1;
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} else
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skb = NULL;
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@ -1283,9 +1283,9 @@ static int pcnet32_rx(struct net_device *dev, int budget)
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* The docs say that the buffer length isn't touched, but Andrew
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* Boyd of QNX reports that some revs of the 79C965 clear it.
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*/
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rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
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rxp->buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
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wmb(); /* Make sure owner changes after others are visible */
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rxp->status = le16_to_cpu(0x8000);
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rxp->status = cpu_to_le16(0x8000);
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entry = (++lp->cur_rx) & lp->rx_mod_mask;
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rxp = &lp->rx_ring[entry];
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}
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@ -1875,15 +1875,15 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
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&& dev->dev_addr[2] == 0x75)
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lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
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lp->init_block->mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
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lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
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lp->init_block->tlen_rlen =
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le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
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cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
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for (i = 0; i < 6; i++)
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lp->init_block->phys_addr[i] = dev->dev_addr[i];
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lp->init_block->filter[0] = 0x00000000;
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lp->init_block->filter[1] = 0x00000000;
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lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
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lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
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lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
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lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
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/* switch pcnet32 to 32bit mode */
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a->write_bcr(ioaddr, 20, 2);
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@ -2274,7 +2274,7 @@ static int pcnet32_open(struct net_device *dev)
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#endif
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lp->init_block->mode =
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le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
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cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
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pcnet32_load_multicast(dev);
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if (pcnet32_init_ring(dev)) {
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@ -2401,10 +2401,10 @@ static int pcnet32_init_ring(struct net_device *dev)
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lp->rx_dma_addr[i] =
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pci_map_single(lp->pci_dev, rx_skbuff->data,
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PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
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lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
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lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
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lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
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lp->rx_ring[i].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
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wmb(); /* Make sure owner changes after all others are visible */
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lp->rx_ring[i].status = le16_to_cpu(0x8000);
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lp->rx_ring[i].status = cpu_to_le16(0x8000);
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}
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/* The Tx buffer address is filled in as needed, but we do need to clear
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* the upper ownership bit. */
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@ -2416,11 +2416,11 @@ static int pcnet32_init_ring(struct net_device *dev)
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}
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lp->init_block->tlen_rlen =
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le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
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cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
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for (i = 0; i < 6; i++)
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lp->init_block->phys_addr[i] = dev->dev_addr[i];
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lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
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lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
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lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
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lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
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wmb(); /* Make sure all changes are visible */
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return 0;
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}
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@ -2529,16 +2529,16 @@ static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
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/* Caution: the write order is important here, set the status
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* with the "ownership" bits last. */
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lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
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lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
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lp->tx_ring[entry].misc = 0x00000000;
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lp->tx_skbuff[entry] = skb;
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lp->tx_dma_addr[entry] =
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pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
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lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
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lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
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wmb(); /* Make sure owner changes after all others are visible */
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lp->tx_ring[entry].status = le16_to_cpu(status);
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lp->tx_ring[entry].status = cpu_to_le16(status);
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lp->cur_tx++;
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lp->stats.tx_bytes += skb->len;
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@ -2709,7 +2709,7 @@ static void pcnet32_load_multicast(struct net_device *dev)
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{
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struct pcnet32_private *lp = netdev_priv(dev);
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volatile struct pcnet32_init_block *ib = lp->init_block;
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volatile u16 *mcast_table = (u16 *) & ib->filter;
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volatile __le16 *mcast_table = (__le16 *)ib->filter;
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struct dev_mc_list *dmi = dev->mc_list;
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unsigned long ioaddr = dev->base_addr;
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char *addrs;
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@ -2718,8 +2718,8 @@ static void pcnet32_load_multicast(struct net_device *dev)
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/* set all multicast bits */
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if (dev->flags & IFF_ALLMULTI) {
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ib->filter[0] = 0xffffffff;
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ib->filter[1] = 0xffffffff;
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ib->filter[0] = cpu_to_le32(~0U);
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ib->filter[1] = cpu_to_le32(~0U);
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lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
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lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
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lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
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@ -2741,9 +2741,7 @@ static void pcnet32_load_multicast(struct net_device *dev)
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crc = ether_crc_le(6, addrs);
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crc = crc >> 26;
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mcast_table[crc >> 4] =
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le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
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(1 << (crc & 0xf)));
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mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
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}
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for (i = 0; i < 4; i++)
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lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
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@ -2769,12 +2767,12 @@ static void pcnet32_set_multicast_list(struct net_device *dev)
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printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
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dev->name);
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lp->init_block->mode =
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le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
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cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
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7);
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lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
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} else {
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lp->init_block->mode =
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le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
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cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
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lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
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pcnet32_load_multicast(dev);
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}
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