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FRV: arrange things such that BRA can reach from the trap table

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Arrange the sections in the FRV arch so that a BRA instruction with a
16-bit displacement can always reach from the trap table to entry.S,
tlb-miss.S and break.S.

The problem otherwise is that the linker can insert sufficient code between
the slots in the trap table and the targets of the branch instructions in
those slots that the displacement field in the instruction isn't
sufficiently large.  This is because the branch targets were in the .text
section along with most of the other code in the kernel.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
David Howells 2007-11-28 16:22:05 -08:00 committed by Linus Torvalds
parent 9e6c1e6333
commit 3c835670ab
4 changed files with 20 additions and 17 deletions
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2
arch/frv/kernel/break.S
View file

@ -63,7 +63,7 @@ __break_trace_through_exceptions:
# entry point for Break Exceptions/Interrupts # entry point for Break Exceptions/Interrupts
# #
############################################################################### ###############################################################################
.text .section .text.break
.balign 4 .balign 4
.globl __entry_break .globl __entry_break
__entry_break: __entry_break:

2
arch/frv/kernel/entry.S
View file

@ -38,7 +38,7 @@
#define nr_syscalls ((syscall_table_size)/4) #define nr_syscalls ((syscall_table_size)/4)
.text .section .text.entry
.balign 4 .balign 4
.macro LEDS val .macro LEDS val

31
arch/frv/kernel/vmlinux.lds.S
View file

@ -76,6 +76,12 @@ SECTIONS
*(.data.init_task) *(.data.init_task)
} }
. = ALIGN(4096);
.data.page_aligned : { *(.data.idt) }
. = ALIGN(L1_CACHE_BYTES);
.data.cacheline_aligned : { *(.data.cacheline_aligned) }
.trap : { .trap : {
/* trap table management - read entry-table.S before modifying */ /* trap table management - read entry-table.S before modifying */
. = ALIGN(8192); . = ALIGN(8192);
@ -86,28 +92,25 @@ SECTIONS
*(.trap.break) *(.trap.break)
} }
. = ALIGN(4096);
.data.page_aligned : { *(.data.idt) }
. = ALIGN(L1_CACHE_BYTES);
.data.cacheline_aligned : { *(.data.cacheline_aligned) }
/* Text and read-only data */ /* Text and read-only data */
. = ALIGN(4); . = ALIGN(4);
_text = .; _text = .;
_stext = .; _stext = .;
.text : { .text : {
*( *(.text.start)
.text.start .text.* *(.text.entry)
#ifdef CONFIG_DEBUG_INFO *(.text.break)
.init.text *(.text.tlbmiss)
.exit.text
.exitcall.exit
#endif
)
TEXT_TEXT TEXT_TEXT
SCHED_TEXT SCHED_TEXT
LOCK_TEXT LOCK_TEXT
#ifdef CONFIG_DEBUG_INFO
*(
.init.text
.exit.text
.exitcall.exit
)
#endif
*(.fixup) *(.fixup)
*(.gnu.warning) *(.gnu.warning)
*(.exitcall.exit) *(.exitcall.exit)

2
arch/frv/mm/tlb-miss.S
View file

@ -16,7 +16,7 @@
#include <asm/highmem.h> #include <asm/highmem.h>
#include <asm/spr-regs.h> #include <asm/spr-regs.h>
.section .text .section .text.tlbmiss
.balign 4 .balign 4
.globl __entry_insn_mmu_miss .globl __entry_insn_mmu_miss