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[libata] Delete pata_it8172 driver
This MIPS platform is going away. Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Jeff Garzik
parent
9359085988
commit
36b35a5be0
3 changed files with 0 additions and 298 deletions
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@ -288,15 +288,6 @@ config PATA_ISAPNP
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If unsure, say N.
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config PATA_IT8172
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tristate "IT8172 PATA support (Very Experimental)"
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depends on PCI && EXPERIMENTAL
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help
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This option enables support for the ITE 8172 PATA controller
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via the new ATA layer.
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If unsure, say N.
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config PATA_IT821X
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tristate "IT821x PATA support (Experimental)"
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depends on PCI && EXPERIMENTAL
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@ -32,7 +32,6 @@ obj-$(CONFIG_PATA_HPT37X) += pata_hpt37x.o
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obj-$(CONFIG_PATA_HPT3X2N) += pata_hpt3x2n.o
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obj-$(CONFIG_PATA_HPT3X3) += pata_hpt3x3.o
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obj-$(CONFIG_PATA_ISAPNP) += pata_isapnp.o
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obj-$(CONFIG_PATA_IT8172) += pata_it8172.o
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obj-$(CONFIG_PATA_IT821X) += pata_it821x.o
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obj-$(CONFIG_PATA_JMICRON) += pata_jmicron.o
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obj-$(CONFIG_PATA_NETCELL) += pata_netcell.o
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@ -1,288 +0,0 @@
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/*
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* pata_it8172.c - IT8172 PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Based heavily on
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*
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* BRIEF MODULE DESCRIPTION
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* IT8172 IDE controller support
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* stevel@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* TODO
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* Check for errata
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* See if we really need to force native mode
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* PIO timings (also lacking in original)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_it8172"
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#define DRV_VERSION "0.3.1"
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static int it8172_pre_reset(struct ata_port *ap)
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{
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static const struct pci_bits it8172_enable_bits[] = {
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{ 0x00, 0, 0x00, 0x00 },
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{ 0x40, 1, 0x00, 0x01 }
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (ap->port_no && !pci_test_config_bits(pdev, &it8172_enable_bits[ap->port_no])) {
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ata_port_disable(ap);
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printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
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return 0;
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}
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ap->cbl = ATA_CBL_PATA40;
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return ata_std_prereset(ap);
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}
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static void it8172_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, it8172_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* it8172_set_pio_timing - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called by both the pio and dma setup functions to set the controller
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* timings for PIO transfers. We must load both the mode number and
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* timing values into the controller.
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*/
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static void it8172_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 reg40;
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pci_read_config_word(pdev, 0x40, ®40);
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/*
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* FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
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* are being left at the default values of 8 PCI clocks (242 nsec
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* for a 33 MHz clock). These can be safely shortened at higher
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* PIO modes. The DIOR/DIOW pulse width and recovery times only
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* apply to PIO modes, not to the DMA modes.
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*/
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/*
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* Enable port 0x44. The IT8172G spec is confused; it calls
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* this register the "Slave IDE Timing Register", but in fact,
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* it controls timing for both master and slave drives.
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*/
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reg40 |= 0x4000;
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if (adev->devno) {
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reg40 &= 0xC006;
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if (pio > 1)
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/* Enable prefetch and IORDY sample-point */
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reg40 |= 0x0060;
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} else {
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reg40 &= 0xC060;
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if (pio > 1)
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/* Enable prefetch and IORDY sample-point */
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reg40 |= 0x0006;
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}
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/* Write back the enables */
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pci_write_config_word(pdev, 0x40, reg40);
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}
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/**
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* it8172_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. We use a shared helper for this
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* as the DMA setup must also adjust the PIO timing information.
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*/
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static void it8172_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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it8172_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
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}
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/**
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* it8172_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the DMA mode setup. We must tune an appropriate PIO
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* mode to match.
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*/
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static void it8172_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = (2 * ap->port_no) + adev->devno;
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u8 reg48, reg4a;
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int pio;
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static const int pio_map[] = { 1, 3, 4};
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/*
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* Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
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* at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
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* transfers on some drives, even though both numbers meet the minimum
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* ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
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* So the faster times are just commented out here. The good news is
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* that the slower cycle time has very little affect on transfer
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* performance.
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*/
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pci_read_config_byte(pdev, 0x48, ®48);
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pci_read_config_byte(pdev, 0x4A, ®4a);
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reg4a &= ~(3 << (4 * dn));
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if (adev->dma_mode >= XFER_UDMA_0) {
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reg48 |= 1 << dn;
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#ifdef UDMA_TIMING_SET
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reg4a |= ((adev->dma_mode - XFER_UDMA_0) << (4 * dn));
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#endif
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pio = 4;
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} else {
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pio = pio_map[adev->dma_mode - XFER_MW_DMA_0];
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reg48 &= ~ (1 << dn);
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}
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pci_write_config_byte(pdev, 0x48, reg48);
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pci_write_config_byte(pdev, 0x4A, reg4a);
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it8172_set_pio_timing(ap, adev, pio);
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}
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static struct scsi_host_template it8172_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations it8172_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = it8172_set_piomode,
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.set_dmamode = it8172_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = it8172_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop
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};
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static int it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static struct ata_port_info info = {
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.sht = &it8172_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x06, /* No MWDMA0 support */
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.udma_mask = 0x7,
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.port_ops = &it8172_port_ops
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};
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static struct ata_port_info *port_info[2] = { &info, &info };
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if ((!(PCI_FUNC(dev->devfn) & 1) ||
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(!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
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return -ENODEV; /* IT8172 is more than an IDE controller */
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return ata_pci_init_one(dev, port_info, 2);
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}
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static struct pci_device_id it8172[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G), },
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{ 0, },
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};
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static struct pci_driver it8172_pci_driver = {
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.name = DRV_NAME,
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.id_table = it8172,
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.probe = it8172_init_one,
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.remove = ata_pci_remove_one
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};
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static int __init it8172_init(void)
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{
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return pci_register_driver(&it8172_pci_driver);
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}
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static void __exit it8172_exit(void)
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{
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pci_unregister_driver(&it8172_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for ITE IT8172");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, it8172);
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MODULE_VERSION(DRV_VERSION);
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module_init(it8172_init);
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module_exit(it8172_exit);
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