mirror of
https://github.com/adulau/aha.git
synced 2024-12-27 03:06:10 +00:00
gpio: add GPIO driver for the Timberdale FPGA
A GPIO driver for the Timberdale FPGA found on the Intel Atom board Russellville. The GPIO driver also has an IRQ-chip to support interrupts on the pins. Signed-off-by: Richard Röjfors <richard.rojfors@mocean-labs.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Richard Röjfors
Linus Torvalds
parent
4efec6272e
commit
35570ac603
4 changed files with 386 additions and 0 deletions
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@ -206,6 +206,12 @@ config GPIO_LANGWELL
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help
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Say Y here to support Intel Moorestown platform GPIO.
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config GPIO_TIMBERDALE
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bool "Support for timberdale GPIO IP"
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depends on MFD_TIMBERDALE && GPIOLIB && HAS_IOMEM
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---help---
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Add support for the GPIO IP in the timberdale FPGA.
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comment "SPI GPIO expanders:"
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config GPIO_MAX7301
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@ -13,6 +13,7 @@ obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o
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obj-$(CONFIG_GPIO_PCA953X) += pca953x.o
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obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
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obj-$(CONFIG_GPIO_PL061) += pl061.o
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obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o
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obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o
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obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o
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obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o
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342
drivers/gpio/timbgpio.c
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342
drivers/gpio/timbgpio.c
Normal file
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@ -0,0 +1,342 @@
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/*
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* timbgpio.c timberdale FPGA GPIO driver
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* Copyright (c) 2009 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Supports:
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* Timberdale FPGA GPIO
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*/
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/timb_gpio.h>
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#include <linux/interrupt.h>
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#define DRIVER_NAME "timb-gpio"
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#define TGPIOVAL 0x00
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#define TGPIODIR 0x04
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#define TGPIO_IER 0x08
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#define TGPIO_ISR 0x0c
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#define TGPIO_IPR 0x10
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#define TGPIO_ICR 0x14
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#define TGPIO_FLR 0x18
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#define TGPIO_LVR 0x1c
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struct timbgpio {
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void __iomem *membase;
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spinlock_t lock; /* mutual exclusion */
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struct gpio_chip gpio;
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int irq_base;
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};
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static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
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unsigned offset, bool enabled)
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{
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struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
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u32 reg;
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spin_lock(&tgpio->lock);
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reg = ioread32(tgpio->membase + offset);
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if (enabled)
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reg |= (1 << index);
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else
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reg &= ~(1 << index);
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iowrite32(reg, tgpio->membase + offset);
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spin_unlock(&tgpio->lock);
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return 0;
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}
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static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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{
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return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
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}
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static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
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{
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struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
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u32 value;
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value = ioread32(tgpio->membase + TGPIOVAL);
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return (value & (1 << nr)) ? 1 : 0;
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}
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static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
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unsigned nr, int val)
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{
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return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
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}
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static void timbgpio_gpio_set(struct gpio_chip *gpio,
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unsigned nr, int val)
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{
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timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
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}
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static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
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{
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struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
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if (tgpio->irq_base <= 0)
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return -EINVAL;
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return tgpio->irq_base + offset;
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}
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/*
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* GPIO IRQ
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*/
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static void timbgpio_irq_disable(unsigned irq)
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{
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struct timbgpio *tgpio = get_irq_chip_data(irq);
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int offset = irq - tgpio->irq_base;
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timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
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}
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static void timbgpio_irq_enable(unsigned irq)
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{
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struct timbgpio *tgpio = get_irq_chip_data(irq);
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int offset = irq - tgpio->irq_base;
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timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
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}
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static int timbgpio_irq_type(unsigned irq, unsigned trigger)
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{
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struct timbgpio *tgpio = get_irq_chip_data(irq);
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int offset = irq - tgpio->irq_base;
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unsigned long flags;
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u32 lvr, flr;
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if (offset < 0 || offset > tgpio->gpio.ngpio)
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return -EINVAL;
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spin_lock_irqsave(&tgpio->lock, flags);
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lvr = ioread32(tgpio->membase + TGPIO_LVR);
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flr = ioread32(tgpio->membase + TGPIO_FLR);
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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flr &= ~(1 << offset);
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if (trigger & IRQ_TYPE_LEVEL_HIGH)
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lvr |= 1 << offset;
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else
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lvr &= ~(1 << offset);
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}
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if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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return -EINVAL;
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else {
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flr |= 1 << offset;
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/* opposite compared to the datasheet, but it mirrors the
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* reality
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*/
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if (trigger & IRQ_TYPE_EDGE_FALLING)
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lvr |= 1 << offset;
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else
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lvr &= ~(1 << offset);
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}
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iowrite32(lvr, tgpio->membase + TGPIO_LVR);
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iowrite32(flr, tgpio->membase + TGPIO_FLR);
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iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
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spin_unlock_irqrestore(&tgpio->lock, flags);
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return 0;
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}
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static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct timbgpio *tgpio = get_irq_data(irq);
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unsigned long ipr;
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int offset;
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desc->chip->ack(irq);
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ipr = ioread32(tgpio->membase + TGPIO_IPR);
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iowrite32(ipr, tgpio->membase + TGPIO_ICR);
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for_each_bit(offset, &ipr, tgpio->gpio.ngpio)
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generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
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}
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static struct irq_chip timbgpio_irqchip = {
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.name = "GPIO",
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.enable = timbgpio_irq_enable,
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.disable = timbgpio_irq_disable,
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.set_type = timbgpio_irq_type,
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};
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static int __devinit timbgpio_probe(struct platform_device *pdev)
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{
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int err, i;
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struct gpio_chip *gc;
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struct timbgpio *tgpio;
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struct resource *iomem;
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struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
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int irq = platform_get_irq(pdev, 0);
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if (!pdata || pdata->nr_pins > 32) {
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err = -EINVAL;
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goto err_mem;
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}
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iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iomem) {
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err = -EINVAL;
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goto err_mem;
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}
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tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
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if (!tgpio) {
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err = -EINVAL;
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goto err_mem;
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}
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tgpio->irq_base = pdata->irq_base;
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spin_lock_init(&tgpio->lock);
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if (!request_mem_region(iomem->start, resource_size(iomem),
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DRIVER_NAME)) {
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err = -EBUSY;
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goto err_request;
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}
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tgpio->membase = ioremap(iomem->start, resource_size(iomem));
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if (!tgpio->membase) {
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err = -ENOMEM;
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goto err_ioremap;
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}
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gc = &tgpio->gpio;
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gc->label = dev_name(&pdev->dev);
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gc->owner = THIS_MODULE;
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gc->dev = &pdev->dev;
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gc->direction_input = timbgpio_gpio_direction_input;
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gc->get = timbgpio_gpio_get;
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gc->direction_output = timbgpio_gpio_direction_output;
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gc->set = timbgpio_gpio_set;
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gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
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gc->dbg_show = NULL;
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gc->base = pdata->gpio_base;
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gc->ngpio = pdata->nr_pins;
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gc->can_sleep = 0;
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err = gpiochip_add(gc);
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if (err)
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goto err_chipadd;
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platform_set_drvdata(pdev, tgpio);
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/* make sure to disable interrupts */
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iowrite32(0x0, tgpio->membase + TGPIO_IER);
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if (irq < 0 || tgpio->irq_base <= 0)
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return 0;
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for (i = 0; i < pdata->nr_pins; i++) {
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set_irq_chip_and_handler_name(tgpio->irq_base + i,
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&timbgpio_irqchip, handle_simple_irq, "mux");
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set_irq_chip_data(tgpio->irq_base + i, tgpio);
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#ifdef CONFIG_ARM
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set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
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#endif
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}
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set_irq_data(irq, tgpio);
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set_irq_chained_handler(irq, timbgpio_irq);
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return 0;
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err_chipadd:
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iounmap(tgpio->membase);
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err_ioremap:
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release_mem_region(iomem->start, resource_size(iomem));
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err_request:
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kfree(tgpio);
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err_mem:
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printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
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return err;
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}
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static int __devexit timbgpio_remove(struct platform_device *pdev)
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{
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int err;
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struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
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struct timbgpio *tgpio = platform_get_drvdata(pdev);
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struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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int irq = platform_get_irq(pdev, 0);
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if (irq >= 0 && tgpio->irq_base > 0) {
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int i;
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for (i = 0; i < pdata->nr_pins; i++) {
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set_irq_chip(tgpio->irq_base + i, NULL);
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set_irq_chip_data(tgpio->irq_base + i, NULL);
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}
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set_irq_handler(irq, NULL);
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set_irq_data(irq, NULL);
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}
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err = gpiochip_remove(&tgpio->gpio);
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if (err)
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printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
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iounmap(tgpio->membase);
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release_mem_region(iomem->start, resource_size(iomem));
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kfree(tgpio);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver timbgpio_platform_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
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},
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.probe = timbgpio_probe,
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.remove = timbgpio_remove,
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};
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/*--------------------------------------------------------------------------*/
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static int __init timbgpio_init(void)
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{
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return platform_driver_register(&timbgpio_platform_driver);
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}
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static void __exit timbgpio_exit(void)
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{
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platform_driver_unregister(&timbgpio_platform_driver);
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}
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module_init(timbgpio_init);
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module_exit(timbgpio_exit);
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MODULE_DESCRIPTION("Timberdale GPIO driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Mocean Laboratories");
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MODULE_ALIAS("platform:"DRIVER_NAME);
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37
include/linux/timb_gpio.h
Normal file
37
include/linux/timb_gpio.h
Normal file
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@ -0,0 +1,37 @@
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/*
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* timb_gpio.h timberdale FPGA GPIO driver, platform data definition
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* Copyright (c) 2009 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _LINUX_TIMB_GPIO_H
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#define _LINUX_TIMB_GPIO_H
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/**
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* struct timbgpio_platform_data - Platform data of the Timberdale GPIO driver
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* @gpio_base The number of the first GPIO pin, set to -1 for
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* dynamic number allocation.
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* @nr_pins Number of pins that is supported by the hardware (1-32)
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* @irq_base If IRQ is supported by the hardware, this is the base
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* number of IRQ:s. One IRQ per pin will be used. Set to
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* -1 if IRQ:s is not supported.
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*/
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struct timbgpio_platform_data {
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int gpio_base;
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int nr_pins;
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int irq_base;
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};
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#endif
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