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Blackfin serial driver: this driver enable SPORTs on Blackfin emulate UART
Signed-off-by: Bryan Wu <bryan.wu@analog.com> Cc: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Bryan Wu
Linus Torvalds
parent
4e68852dca
commit
2f3517418d
5 changed files with 725 additions and 2 deletions
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@ -1355,4 +1355,47 @@ config SERIAL_SC26XX_CONSOLE
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help
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help
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Support for Console on SC2681/SC2692 serial ports.
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Support for Console on SC2681/SC2692 serial ports.
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config SERIAL_BFIN_SPORT
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tristate "Blackfin SPORT emulate UART (EXPERIMENTAL)"
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depends on BFIN && EXPERIMENTAL
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select SERIAL_CORE
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help
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Enble support SPORT emulate UART on Blackfin series.
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To compile this driver as a module, choose M here: the
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module will be called bfin_sport_uart.
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choice
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prompt "Baud rate for Blackfin SPORT UART"
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depends on SERIAL_BFIN_SPORT
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default SERIAL_SPORT_BAUD_RATE_57600
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help
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Choose a baud rate for the SPORT UART, other uart settings are
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8 bit, 1 stop bit, no parity, no flow control.
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config SERIAL_SPORT_BAUD_RATE_115200
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bool "115200"
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config SERIAL_SPORT_BAUD_RATE_57600
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bool "57600"
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config SERIAL_SPORT_BAUD_RATE_38400
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bool "38400"
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config SERIAL_SPORT_BAUD_RATE_19200
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bool "19200"
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config SERIAL_SPORT_BAUD_RATE_9600
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bool "9600"
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endchoice
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config SPORT_BAUD_RATE
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int
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depends on SERIAL_BFIN_SPORT
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default 115200 if (SERIAL_SPORT_BAUD_RATE_115200)
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default 57600 if (SERIAL_SPORT_BAUD_RATE_57600)
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default 38400 if (SERIAL_SPORT_BAUD_RATE_38400)
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default 19200 if (SERIAL_SPORT_BAUD_RATE_19200)
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default 9600 if (SERIAL_SPORT_BAUD_RATE_9600)
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endmenu
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endmenu
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@ -27,6 +27,7 @@ obj-$(CONFIG_SERIAL_PXA) += pxa.o
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obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
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obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
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obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
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obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
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obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
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obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
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obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
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obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
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obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
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obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
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obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
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obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
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obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
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614
drivers/serial/bfin_sport_uart.c
Normal file
614
drivers/serial/bfin_sport_uart.c
Normal file
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@ -0,0 +1,614 @@
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/*
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* File: linux/drivers/serial/bfin_sport_uart.c
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*
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* Based on: drivers/serial/bfin_5xx.c by Aubrey Li.
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* Author: Roy Huang <roy.huang@analog.com>
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*
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* Created: Nov 22, 2006
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* Copyright: (c) 2006-2007 Analog Devices Inc.
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* Description: this driver enable SPORTs on Blackfin emulate UART.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* This driver and the hardware supported are in term of EE-191 of ADI.
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* http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
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* This application note describe how to implement a UART on a Sharc DSP,
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* but this driver is implemented on Blackfin Processor.
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*/
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/* After reset, there is a prelude of low level pulse when transmit data first
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* time. No addtional pulse in following transmit.
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* According to document:
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* The SPORTs are ready to start transmitting or receiving data no later than
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* three serial clock cycles after they are enabled in the SPORTx_TCR1 or
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* SPORTx_RCR1 register. No serial clock cycles are lost from this point on.
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* The first internal frame sync will occur one frame sync delay after the
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* SPORTs are ready. External frame syncs can occur as soon as the SPORT is
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* ready.
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*/
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/* Thanks to Axel Alatalo <axel@rubico.se> for fixing sport rx bug. Sometimes
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* sport receives data incorrectly. The following is Axel's words.
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* As EE-191, sport rx samples 3 times of the UART baudrate and takes the
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* middle smaple of every 3 samples as the data bit. For a 8-N-1 UART setting,
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* 30 samples will be required for a byte. If transmitter sends a 1/3 bit short
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* byte due to buadrate drift, then the 30th sample of a byte, this sample is
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* also the third sample of the stop bit, will happens on the immediately
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* following start bit which will be thrown away and missed. Thus since parts
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* of the startbit will be missed and the receiver will begin to drift, the
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* effect accumulates over time until synchronization is lost.
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* If only require 2 samples of the stopbit (by sampling in total 29 samples),
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* then a to short byte as in the case above will be tolerated. Then the 1/3
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* early startbit will trigger a framesync since the last read is complete
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* after only 2/3 stopbit and framesync is active during the last 1/3 looking
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* for a possible early startbit. */
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//#define DEBUG
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/platform_device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <asm/delay.h>
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#include <asm/portmux.h>
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#include "bfin_sport_uart.h"
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unsigned short bfin_uart_pin_req_sport0[] =
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{P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \
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P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0};
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unsigned short bfin_uart_pin_req_sport1[] =
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{P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \
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P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0};
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#define DRV_NAME "bfin-sport-uart"
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struct sport_uart_port {
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struct uart_port port;
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char *name;
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int tx_irq;
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int rx_irq;
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int err_irq;
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};
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static void sport_uart_tx_chars(struct sport_uart_port *up);
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static void sport_stop_tx(struct uart_port *port);
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static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
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{
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pr_debug("%s value:%x\n", __FUNCTION__, value);
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/* Place a Start and Stop bit */
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__asm__ volatile (
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"R2 = b#01111111100;\n\t"
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"R3 = b#10000000001;\n\t"
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"%0 <<= 2;\n\t"
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"%0 = %0 & R2;\n\t"
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"%0 = %0 | R3;\n\t"
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:"=r"(value)
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:"0"(value)
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:"R2", "R3");
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pr_debug("%s value:%x\n", __FUNCTION__, value);
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SPORT_PUT_TX(up, value);
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}
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static inline unsigned int rx_one_byte(struct sport_uart_port *up)
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{
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unsigned int value, extract;
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value = SPORT_GET_RX32(up);
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pr_debug("%s value:%x\n", __FUNCTION__, value);
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/* Extract 8 bits data */
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__asm__ volatile (
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"R5 = 0;\n\t"
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"P0 = 8;\n\t"
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"R1 = 0x1801(Z);\n\t"
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"R3 = 0x0300(Z);\n\t"
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"R4 = 0;\n\t"
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"LSETUP(loop_s, loop_e) LC0 = P0;\nloop_s:\t"
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"R2 = extract(%1, R1.L)(Z);\n\t"
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"R2 <<= R4;\n\t"
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"R5 = R5 | R2;\n\t"
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"R1 = R1 - R3;\nloop_e:\t"
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"R4 += 1;\n\t"
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"%0 = R5;\n\t"
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:"=r"(extract)
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:"r"(value)
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:"P0", "R1", "R2","R3","R4", "R5");
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pr_debug(" extract:%x\n", extract);
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return extract;
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}
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static int sport_uart_setup(struct sport_uart_port *up, int sclk, int baud_rate)
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{
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int tclkdiv, tfsdiv, rclkdiv;
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/* Set TCR1 and TCR2 */
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SPORT_PUT_TCR1(up, (LTFS | ITFS | TFSR | TLSBIT | ITCLK));
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SPORT_PUT_TCR2(up, 10);
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pr_debug("%s TCR1:%x, TCR2:%x\n", __FUNCTION__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
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/* Set RCR1 and RCR2 */
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SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
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SPORT_PUT_RCR2(up, 28);
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pr_debug("%s RCR1:%x, RCR2:%x\n", __FUNCTION__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
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tclkdiv = sclk/(2 * baud_rate) - 1;
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tfsdiv = 12;
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rclkdiv = sclk/(2 * baud_rate * 3) - 1;
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SPORT_PUT_TCLKDIV(up, tclkdiv);
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SPORT_PUT_TFSDIV(up, tfsdiv);
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SPORT_PUT_RCLKDIV(up, rclkdiv);
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SSYNC();
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pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, tfsdiv:%d, rclkdiv:%d\n",
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__FUNCTION__, sclk, baud_rate, tclkdiv, tfsdiv, rclkdiv);
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return 0;
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}
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static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
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{
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struct sport_uart_port *up = dev_id;
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struct tty_struct *tty = up->port.info->tty;
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unsigned int ch;
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do {
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ch = rx_one_byte(up);
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up->port.icount.rx++;
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if (uart_handle_sysrq_char(&up->port, ch))
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;
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else
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tty_insert_flip_char(tty, ch, TTY_NORMAL);
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} while (SPORT_GET_STAT(up) & RXNE);
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tty_flip_buffer_push(tty);
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return IRQ_HANDLED;
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}
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static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
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{
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sport_uart_tx_chars(dev_id);
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return IRQ_HANDLED;
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}
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static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
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{
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struct sport_uart_port *up = dev_id;
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struct tty_struct *tty = up->port.info->tty;
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unsigned int stat = SPORT_GET_STAT(up);
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/* Overflow in RX FIFO */
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if (stat & ROVF) {
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up->port.icount.overrun++;
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
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}
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/* These should not happen */
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if (stat & (TOVF | TUVF | RUVF)) {
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printk(KERN_ERR "SPORT Error:%s %s %s\n",
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(stat & TOVF)?"TX overflow":"",
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(stat & TUVF)?"TX underflow":"",
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(stat & RUVF)?"RX underflow":"");
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SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
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SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
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}
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SSYNC();
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return IRQ_HANDLED;
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}
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/* Reqeust IRQ, Setup clock */
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static int sport_startup(struct uart_port *port)
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{
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struct sport_uart_port *up = (struct sport_uart_port *)port;
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char buffer[20];
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int retval;
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pr_debug("%s enter\n", __FUNCTION__);
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memset(buffer, 20, '\0');
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snprintf(buffer, 20, "%s rx", up->name);
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retval = request_irq(up->rx_irq, sport_uart_rx_irq, IRQF_SAMPLE_RANDOM, buffer, up);
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if (retval) {
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printk(KERN_ERR "Unable to request interrupt %s\n", buffer);
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return retval;
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}
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snprintf(buffer, 20, "%s tx", up->name);
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retval = request_irq(up->tx_irq, sport_uart_tx_irq, IRQF_SAMPLE_RANDOM, buffer, up);
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if (retval) {
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printk(KERN_ERR "Unable to request interrupt %s\n", buffer);
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goto fail1;
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}
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snprintf(buffer, 20, "%s err", up->name);
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retval = request_irq(up->err_irq, sport_uart_err_irq, IRQF_SAMPLE_RANDOM, buffer, up);
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if (retval) {
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printk(KERN_ERR "Unable to request interrupt %s\n", buffer);
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goto fail2;
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}
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if (port->line) {
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if (peripheral_request_list(bfin_uart_pin_req_sport1, DRV_NAME))
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goto fail3;
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} else {
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if (peripheral_request_list(bfin_uart_pin_req_sport0, DRV_NAME))
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goto fail3;
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}
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sport_uart_setup(up, get_sclk(), port->uartclk);
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/* Enable receive interrupt */
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SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) | RSPEN));
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SSYNC();
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return 0;
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fail3:
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printk(KERN_ERR DRV_NAME
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": Requesting Peripherals failed\n");
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free_irq(up->err_irq, up);
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fail2:
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free_irq(up->tx_irq, up);
|
||||||
|
fail1:
|
||||||
|
free_irq(up->rx_irq, up);
|
||||||
|
|
||||||
|
return retval;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_uart_tx_chars(struct sport_uart_port *up)
|
||||||
|
{
|
||||||
|
struct circ_buf *xmit = &up->port.info->xmit;
|
||||||
|
|
||||||
|
if (SPORT_GET_STAT(up) & TXF)
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (up->port.x_char) {
|
||||||
|
tx_one_byte(up, up->port.x_char);
|
||||||
|
up->port.icount.tx++;
|
||||||
|
up->port.x_char = 0;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
|
||||||
|
sport_stop_tx(&up->port);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
|
||||||
|
tx_one_byte(up, xmit->buf[xmit->tail]);
|
||||||
|
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
|
||||||
|
up->port.icount.tx++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
||||||
|
uart_write_wakeup(&up->port);
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int sport_tx_empty(struct uart_port *port)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||||
|
unsigned int stat;
|
||||||
|
|
||||||
|
stat = SPORT_GET_STAT(up);
|
||||||
|
pr_debug("%s stat:%04x\n", __FUNCTION__, stat);
|
||||||
|
if (stat & TXHRE) {
|
||||||
|
return TIOCSER_TEMT;
|
||||||
|
} else
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int sport_get_mctrl(struct uart_port *port)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
return (TIOCM_CTS | TIOCM_CD | TIOCM_DSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_stop_tx(struct uart_port *port)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||||
|
unsigned int stat;
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
|
||||||
|
stat = SPORT_GET_STAT(up);
|
||||||
|
while(!(stat & TXHRE)) {
|
||||||
|
udelay(1);
|
||||||
|
stat = SPORT_GET_STAT(up);
|
||||||
|
}
|
||||||
|
/* Although the hold register is empty, last byte is still in shift
|
||||||
|
* register and not sent out yet. If baud rate is lower than default,
|
||||||
|
* delay should be longer. For example, if the baud rate is 9600,
|
||||||
|
* the delay must be at least 2ms by experience */
|
||||||
|
udelay(500);
|
||||||
|
|
||||||
|
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
|
||||||
|
SSYNC();
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_start_tx(struct uart_port *port)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
/* Write data into SPORT FIFO before enable SPROT to transmit */
|
||||||
|
sport_uart_tx_chars(up);
|
||||||
|
|
||||||
|
/* Enable transmit, then an interrupt will generated */
|
||||||
|
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
|
||||||
|
SSYNC();
|
||||||
|
pr_debug("%s exit\n", __FUNCTION__);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_stop_rx(struct uart_port *port)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
/* Disable sport to stop rx */
|
||||||
|
SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
|
||||||
|
SSYNC();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_enable_ms(struct uart_port *port)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_break_ctl(struct uart_port *port, int break_state)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_shutdown(struct uart_port *port)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
|
||||||
|
/* Disable sport */
|
||||||
|
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
|
||||||
|
SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
|
||||||
|
SSYNC();
|
||||||
|
|
||||||
|
if (port->line) {
|
||||||
|
peripheral_free_list(bfin_uart_pin_req_sport1);
|
||||||
|
} else {
|
||||||
|
peripheral_free_list(bfin_uart_pin_req_sport0);
|
||||||
|
}
|
||||||
|
|
||||||
|
free_irq(up->rx_irq, up);
|
||||||
|
free_irq(up->tx_irq, up);
|
||||||
|
free_irq(up->err_irq, up);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_set_termios(struct uart_port *port,
|
||||||
|
struct termios *termios, struct termios *old)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter, c_cflag:%08x\n", __FUNCTION__, termios->c_cflag);
|
||||||
|
uart_update_timeout(port, CS8 ,port->uartclk);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char *sport_type(struct uart_port *port)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
return up->name;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_release_port(struct uart_port *port)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int sport_request_port(struct uart_port *port)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sport_config_port(struct uart_port *port, int flags)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
up->port.type = PORT_BFIN_SPORT;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct uart_ops sport_uart_ops = {
|
||||||
|
.tx_empty = sport_tx_empty,
|
||||||
|
.set_mctrl = sport_set_mctrl,
|
||||||
|
.get_mctrl = sport_get_mctrl,
|
||||||
|
.stop_tx = sport_stop_tx,
|
||||||
|
.start_tx = sport_start_tx,
|
||||||
|
.stop_rx = sport_stop_rx,
|
||||||
|
.enable_ms = sport_enable_ms,
|
||||||
|
.break_ctl = sport_break_ctl,
|
||||||
|
.startup = sport_startup,
|
||||||
|
.shutdown = sport_shutdown,
|
||||||
|
.set_termios = sport_set_termios,
|
||||||
|
.type = sport_type,
|
||||||
|
.release_port = sport_release_port,
|
||||||
|
.request_port = sport_request_port,
|
||||||
|
.config_port = sport_config_port,
|
||||||
|
.verify_port = sport_verify_port,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct sport_uart_port sport_uart_ports[] = {
|
||||||
|
{ /* SPORT 0 */
|
||||||
|
.name = "SPORT0",
|
||||||
|
.tx_irq = IRQ_SPORT0_TX,
|
||||||
|
.rx_irq = IRQ_SPORT0_RX,
|
||||||
|
.err_irq= IRQ_SPORT0_ERROR,
|
||||||
|
.port = {
|
||||||
|
.type = PORT_BFIN_SPORT,
|
||||||
|
.iotype = UPIO_MEM,
|
||||||
|
.membase = (void __iomem *)SPORT0_TCR1,
|
||||||
|
.mapbase = SPORT0_TCR1,
|
||||||
|
.irq = IRQ_SPORT0_RX,
|
||||||
|
.uartclk = CONFIG_SPORT_BAUD_RATE,
|
||||||
|
.fifosize = 8,
|
||||||
|
.ops = &sport_uart_ops,
|
||||||
|
.line = 0,
|
||||||
|
},
|
||||||
|
}, { /* SPORT 1 */
|
||||||
|
.name = "SPORT1",
|
||||||
|
.tx_irq = IRQ_SPORT1_TX,
|
||||||
|
.rx_irq = IRQ_SPORT1_RX,
|
||||||
|
.err_irq= IRQ_SPORT1_ERROR,
|
||||||
|
.port = {
|
||||||
|
.type = PORT_BFIN_SPORT,
|
||||||
|
.iotype = UPIO_MEM,
|
||||||
|
.membase = (void __iomem *)SPORT1_TCR1,
|
||||||
|
.mapbase = SPORT1_TCR1,
|
||||||
|
.irq = IRQ_SPORT1_RX,
|
||||||
|
.uartclk = CONFIG_SPORT_BAUD_RATE,
|
||||||
|
.fifosize = 8,
|
||||||
|
.ops = &sport_uart_ops,
|
||||||
|
.line = 1,
|
||||||
|
},
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct uart_driver sport_uart_reg = {
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.driver_name = "SPORT-UART",
|
||||||
|
.dev_name = "ttySS",
|
||||||
|
.major = 204,
|
||||||
|
.minor = 84,
|
||||||
|
.nr = ARRAY_SIZE(sport_uart_ports),
|
||||||
|
.cons = NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int sport_uart_suspend(struct platform_device *dev, pm_message_t state)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *sport = platform_get_drvdata(dev);
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
if (sport)
|
||||||
|
uart_suspend_port(&sport_uart_reg, &sport->port);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int sport_uart_resume(struct platform_device *dev)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *sport = platform_get_drvdata(dev);
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
if (sport)
|
||||||
|
uart_resume_port(&sport_uart_reg, &sport->port);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int sport_uart_probe(struct platform_device *dev)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
sport_uart_ports[dev->id].port.dev = &dev->dev;
|
||||||
|
uart_add_one_port(&sport_uart_reg, &sport_uart_ports[dev->id].port);
|
||||||
|
platform_set_drvdata(dev, &sport_uart_ports[dev->id]);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int sport_uart_remove(struct platform_device *dev)
|
||||||
|
{
|
||||||
|
struct sport_uart_port *sport = platform_get_drvdata(dev);
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
platform_set_drvdata(dev, NULL);
|
||||||
|
|
||||||
|
if (sport)
|
||||||
|
uart_remove_one_port(&sport_uart_reg, &sport->port);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct platform_driver sport_uart_driver = {
|
||||||
|
.probe = sport_uart_probe,
|
||||||
|
.remove = sport_uart_remove,
|
||||||
|
.suspend = sport_uart_suspend,
|
||||||
|
.resume = sport_uart_resume,
|
||||||
|
.driver = {
|
||||||
|
.name = DRV_NAME,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init sport_uart_init(void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
ret = uart_register_driver(&sport_uart_reg);
|
||||||
|
if (ret != 0) {
|
||||||
|
printk(KERN_ERR "Failed to register %s:%d\n",
|
||||||
|
sport_uart_reg.driver_name, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = platform_driver_register(&sport_uart_driver);
|
||||||
|
if (ret != 0) {
|
||||||
|
printk(KERN_ERR "Failed to register sport uart driver:%d\n", ret);
|
||||||
|
uart_unregister_driver(&sport_uart_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
pr_debug("%s exit\n", __FUNCTION__);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exit sport_uart_exit(void)
|
||||||
|
{
|
||||||
|
pr_debug("%s enter\n", __FUNCTION__);
|
||||||
|
platform_driver_unregister(&sport_uart_driver);
|
||||||
|
uart_unregister_driver(&sport_uart_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
module_init(sport_uart_init);
|
||||||
|
module_exit(sport_uart_exit);
|
||||||
|
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
63
drivers/serial/bfin_sport_uart.h
Normal file
63
drivers/serial/bfin_sport_uart.h
Normal file
|
|
@ -0,0 +1,63 @@
|
||||||
|
/*
|
||||||
|
* File: linux/drivers/serial/bfin_sport_uart.h
|
||||||
|
*
|
||||||
|
* Based on: include/asm-blackfin/mach-533/bfin_serial_5xx.h
|
||||||
|
* Author: Roy Huang <roy.huang>analog.com>
|
||||||
|
*
|
||||||
|
* Created: Nov 22, 2006
|
||||||
|
* Copyright: (C) Analog Device Inc.
|
||||||
|
* Description: this driver enable SPORTs on Blackfin emulate UART.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
|
||||||
|
#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
|
||||||
|
#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
|
||||||
|
#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
|
||||||
|
#define OFFSET_TX 0x10 /* Transmit Data Register */
|
||||||
|
#define OFFSET_RX 0x18 /* Receive Data Register */
|
||||||
|
#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
|
||||||
|
#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
|
||||||
|
#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
|
||||||
|
#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
|
||||||
|
#define OFFSET_STAT 0x30 /* Status Register */
|
||||||
|
|
||||||
|
#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
|
||||||
|
#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
|
||||||
|
#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
|
||||||
|
#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
|
||||||
|
#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
|
||||||
|
#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
|
||||||
|
#define SPORT_GET_RX32(sport) bfin_read32(((sport)->port.membase + OFFSET_RX))
|
||||||
|
#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
|
||||||
|
#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
|
||||||
|
#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
|
||||||
|
#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
|
||||||
|
#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
|
||||||
|
|
||||||
|
#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
|
||||||
|
#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
|
||||||
|
#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
|
||||||
|
#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
|
||||||
|
#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
|
||||||
|
#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
|
||||||
|
#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
|
||||||
|
#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
|
||||||
|
#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
|
||||||
|
#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
|
||||||
|
#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
|
||||||
|
|
@ -149,13 +149,15 @@
|
||||||
/* Freescale ColdFire */
|
/* Freescale ColdFire */
|
||||||
#define PORT_MCF 78
|
#define PORT_MCF 78
|
||||||
|
|
||||||
#define PORT_SC26XX 79
|
/* Blackfin SPORT */
|
||||||
|
#define PORT_BFIN_SPORT 79
|
||||||
|
|
||||||
/* MN10300 on-chip UART numbers */
|
/* MN10300 on-chip UART numbers */
|
||||||
#define PORT_MN10300 80
|
#define PORT_MN10300 80
|
||||||
#define PORT_MN10300_CTS 81
|
#define PORT_MN10300_CTS 81
|
||||||
|
|
||||||
|
#define PORT_SC26XX 82
|
||||||
|
|
||||||
#ifdef __KERNEL__
|
#ifdef __KERNEL__
|
||||||
|
|
||||||
#include <linux/compiler.h>
|
#include <linux/compiler.h>
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue