mirror of
https://github.com/adulau/aha.git
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ide: move SFF DMA code to ide-dma-sff.c
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
parent
db3f99ef7c
commit
2dbe7e919e
4 changed files with 362 additions and 362 deletions
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@ -12,6 +12,7 @@ ide-core-$(CONFIG_IDE_TIMINGS) += ide-timings.o
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ide-core-$(CONFIG_IDE_ATAPI) += ide-atapi.o
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ide-core-$(CONFIG_BLK_DEV_IDEPCI) += setup-pci.o
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ide-core-$(CONFIG_BLK_DEV_IDEDMA) += ide-dma.o
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ide-core-$(CONFIG_BLK_DEV_IDEDMA_SFF) += ide-dma-sff.o
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ide-core-$(CONFIG_IDE_PROC_FS) += ide-proc.o
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ide-core-$(CONFIG_BLK_DEV_IDEACPI) += ide-acpi.o
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356
drivers/ide/ide-dma-sff.c
Normal file
356
drivers/ide/ide-dma-sff.c
Normal file
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@ -0,0 +1,356 @@
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/ide.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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/**
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* config_drive_for_dma - attempt to activate IDE DMA
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* @drive: the drive to place in DMA mode
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*
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* If the drive supports at least mode 2 DMA or UDMA of any kind
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* then attempt to place it into DMA mode. Drives that are known to
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* support DMA but predate the DMA properties or that are known
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* to have DMA handling bugs are also set up appropriately based
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* on the good/bad drive lists.
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*/
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int config_drive_for_dma(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u16 *id = drive->id;
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if (drive->media != ide_disk) {
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if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
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return 0;
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}
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/*
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* Enable DMA on any drive that has
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* UltraDMA (mode 0/1/2/3/4/5/6) enabled
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*/
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if ((id[ATA_ID_FIELD_VALID] & 4) &&
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((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
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return 1;
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/*
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* Enable DMA on any drive that has mode2 DMA
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* (multi or single) enabled
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*/
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if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */
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if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||
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(id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
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return 1;
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/* Consult the list of known "good" drives */
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if (ide_dma_good_drive(drive))
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return 1;
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return 0;
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}
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/**
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* ide_dma_host_set - Enable/disable DMA on a host
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* @drive: drive to control
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*
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* Enable/disable DMA on an IDE controller following generic
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* bus-mastering IDE controller behaviour.
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*/
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void ide_dma_host_set(ide_drive_t *drive, int on)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 unit = drive->dn & 1;
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u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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if (on)
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dma_stat |= (1 << (5 + unit));
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else
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dma_stat &= ~(1 << (5 + unit));
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if (hwif->host_flags & IDE_HFLAG_MMIO)
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writeb(dma_stat,
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(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
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else
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outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
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}
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EXPORT_SYMBOL_GPL(ide_dma_host_set);
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/**
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* ide_build_dmatable - build IDE DMA table
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*
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* ide_build_dmatable() prepares a dma request. We map the command
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* to get the pci bus addresses of the buffers and then build up
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* the PRD table that the IDE layer wants to be fed.
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*
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* Most chipsets correctly interpret a length of 0x0000 as 64KB,
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* but at least one (e.g. CS5530) misinterprets it as zero (!).
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* So we break the 64KB entry into two 32KB entries instead.
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*
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* Returns the number of built PRD entries if all went okay,
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* returns 0 otherwise.
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*
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* May also be invoked from trm290.c
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*/
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int ide_build_dmatable(ide_drive_t *drive, struct request *rq)
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{
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ide_hwif_t *hwif = drive->hwif;
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__le32 *table = (__le32 *)hwif->dmatable_cpu;
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unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
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unsigned int count = 0;
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int i;
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struct scatterlist *sg;
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hwif->sg_nents = ide_build_sglist(drive, rq);
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if (hwif->sg_nents == 0)
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return 0;
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for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) {
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u32 cur_addr, cur_len, xcount, bcount;
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cur_addr = sg_dma_address(sg);
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cur_len = sg_dma_len(sg);
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/*
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* Fill in the dma table, without crossing any 64kB boundaries.
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* Most hardware requires 16-bit alignment of all blocks,
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* but the trm290 requires 32-bit alignment.
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*/
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while (cur_len) {
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if (count++ >= PRD_ENTRIES)
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goto use_pio_instead;
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bcount = 0x10000 - (cur_addr & 0xffff);
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if (bcount > cur_len)
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bcount = cur_len;
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*table++ = cpu_to_le32(cur_addr);
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xcount = bcount & 0xffff;
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if (is_trm290)
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xcount = ((xcount >> 2) - 1) << 16;
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if (xcount == 0x0000) {
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if (count++ >= PRD_ENTRIES)
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goto use_pio_instead;
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*table++ = cpu_to_le32(0x8000);
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*table++ = cpu_to_le32(cur_addr + 0x8000);
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xcount = 0x8000;
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}
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*table++ = cpu_to_le32(xcount);
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cur_addr += bcount;
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cur_len -= bcount;
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}
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}
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if (count) {
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if (!is_trm290)
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*--table |= cpu_to_le32(0x80000000);
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return count;
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}
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use_pio_instead:
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printk(KERN_ERR "%s: %s\n", drive->name,
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count ? "DMA table too small" : "empty DMA table?");
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ide_destroy_dmatable(drive);
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return 0; /* revert to PIO for this request */
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}
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EXPORT_SYMBOL_GPL(ide_build_dmatable);
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/**
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* ide_dma_setup - begin a DMA phase
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* @drive: target device
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*
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* Build an IDE DMA PRD (IDE speak for scatter gather table)
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* and then set up the DMA transfer registers for a device
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* that follows generic IDE PCI DMA behaviour. Controllers can
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* override this function if they need to
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*
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* Returns 0 on success. If a PIO fallback is required then 1
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* is returned.
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*/
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int ide_dma_setup(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct request *rq = hwif->hwgroup->rq;
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unsigned int reading;
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u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
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u8 dma_stat;
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if (rq_data_dir(rq))
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reading = 0;
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else
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reading = 1 << 3;
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/* fall back to pio! */
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if (!ide_build_dmatable(drive, rq)) {
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ide_map_sg(drive, rq);
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return 1;
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}
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/* PRD table */
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if (hwif->host_flags & IDE_HFLAG_MMIO)
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writel(hwif->dmatable_dma,
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(void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
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else
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outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
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/* specify r/w */
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if (mmio)
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writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
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else
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outb(reading, hwif->dma_base + ATA_DMA_CMD);
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/* read DMA status for INTR & ERROR flags */
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dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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/* clear INTR & ERROR flags */
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if (mmio)
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writeb(dma_stat | 6,
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(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
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else
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outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
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drive->waiting_for_dma = 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ide_dma_setup);
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/**
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* dma_timer_expiry - handle a DMA timeout
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* @drive: Drive that timed out
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*
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* An IDE DMA transfer timed out. In the event of an error we ask
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* the driver to resolve the problem, if a DMA transfer is still
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* in progress we continue to wait (arguably we need to add a
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* secondary 'I don't care what the drive thinks' timeout here)
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* Finally if we have an interrupt we let it complete the I/O.
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* But only one time - we clear expiry and if it's still not
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* completed after WAIT_CMD, we error and retry in PIO.
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* This can occur if an interrupt is lost or due to hang or bugs.
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*/
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static int dma_timer_expiry(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
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drive->name, __func__, dma_stat);
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if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
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return WAIT_CMD;
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hwif->hwgroup->expiry = NULL; /* one free ride for now */
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/* 1 dmaing, 2 error, 4 intr */
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if (dma_stat & 2) /* ERROR */
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return -1;
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if (dma_stat & 1) /* DMAing */
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return WAIT_CMD;
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if (dma_stat & 4) /* Got an Interrupt */
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return WAIT_CMD;
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return 0; /* Status is unknown -- reset the bus */
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}
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void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
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{
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/* issue cmd to drive */
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ide_execute_command(drive, command, &ide_dma_intr, 2 * WAIT_CMD,
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dma_timer_expiry);
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}
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EXPORT_SYMBOL_GPL(ide_dma_exec_cmd);
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void ide_dma_start(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 dma_cmd;
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/* Note that this is done *after* the cmd has
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* been issued to the drive, as per the BM-IDE spec.
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* The Promise Ultra33 doesn't work correctly when
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* we do this part before issuing the drive cmd.
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*/
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if (hwif->host_flags & IDE_HFLAG_MMIO) {
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dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
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/* start DMA */
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writeb(dma_cmd | 1,
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(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
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} else {
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dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
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outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD);
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}
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wmb();
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}
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EXPORT_SYMBOL_GPL(ide_dma_start);
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/* returns 1 on error, 0 otherwise */
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int ide_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
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u8 dma_stat = 0, dma_cmd = 0;
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drive->waiting_for_dma = 0;
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if (mmio) {
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/* get DMA command mode */
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dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
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/* stop DMA */
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writeb(dma_cmd & ~1,
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(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
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} else {
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dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
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outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
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}
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/* get DMA status */
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dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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if (mmio)
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/* clear the INTR & ERROR bits */
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writeb(dma_stat | 6,
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(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
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else
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outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
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/* purge DMA mappings */
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ide_destroy_dmatable(drive);
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/* verify good DMA status */
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wmb();
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return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
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}
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EXPORT_SYMBOL_GPL(ide_dma_end);
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/* returns 1 if dma irq issued, 0 otherwise */
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int ide_dma_test_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
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/* return 1 if INTR asserted */
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if ((dma_stat & 4) == 4)
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return 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ide_dma_test_irq);
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const struct ide_dma_ops sff_dma_ops = {
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.dma_host_set = ide_dma_host_set,
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.dma_setup = ide_dma_setup,
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.dma_exec_cmd = ide_dma_exec_cmd,
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.dma_start = ide_dma_start,
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.dma_end = ide_dma_end,
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.dma_test_irq = ide_dma_test_irq,
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.dma_timeout = ide_dma_timeout,
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.dma_lost_irq = ide_dma_lost_irq,
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};
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EXPORT_SYMBOL_GPL(sff_dma_ops);
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@ -33,7 +33,6 @@
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#include <linux/ide.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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static const struct drive_list_entry drive_whitelist[] = {
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{ "Micropolis 2112A" , NULL },
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@ -109,7 +108,7 @@ ide_startstop_t ide_dma_intr(ide_drive_t *drive)
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}
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EXPORT_SYMBOL_GPL(ide_dma_intr);
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static int ide_dma_good_drive(ide_drive_t *drive)
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int ide_dma_good_drive(ide_drive_t *drive)
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{
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return ide_in_drive_list(drive->id, drive_whitelist);
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}
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@ -142,90 +141,6 @@ int ide_build_sglist(ide_drive_t *drive, struct request *rq)
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}
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EXPORT_SYMBOL_GPL(ide_build_sglist);
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#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
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/**
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* ide_build_dmatable - build IDE DMA table
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*
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* ide_build_dmatable() prepares a dma request. We map the command
|
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* to get the pci bus addresses of the buffers and then build up
|
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* the PRD table that the IDE layer wants to be fed.
|
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*
|
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* Most chipsets correctly interpret a length of 0x0000 as 64KB,
|
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* but at least one (e.g. CS5530) misinterprets it as zero (!).
|
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* So we break the 64KB entry into two 32KB entries instead.
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*
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* Returns the number of built PRD entries if all went okay,
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* returns 0 otherwise.
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*
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* May also be invoked from trm290.c
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*/
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int ide_build_dmatable(ide_drive_t *drive, struct request *rq)
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{
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ide_hwif_t *hwif = drive->hwif;
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__le32 *table = (__le32 *)hwif->dmatable_cpu;
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unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
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unsigned int count = 0;
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int i;
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struct scatterlist *sg;
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hwif->sg_nents = ide_build_sglist(drive, rq);
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if (hwif->sg_nents == 0)
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return 0;
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for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) {
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u32 cur_addr, cur_len, xcount, bcount;
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cur_addr = sg_dma_address(sg);
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cur_len = sg_dma_len(sg);
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/*
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* Fill in the dma table, without crossing any 64kB boundaries.
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* Most hardware requires 16-bit alignment of all blocks,
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* but the trm290 requires 32-bit alignment.
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*/
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while (cur_len) {
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if (count++ >= PRD_ENTRIES)
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goto use_pio_instead;
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bcount = 0x10000 - (cur_addr & 0xffff);
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if (bcount > cur_len)
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bcount = cur_len;
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*table++ = cpu_to_le32(cur_addr);
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xcount = bcount & 0xffff;
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if (is_trm290)
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xcount = ((xcount >> 2) - 1) << 16;
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if (xcount == 0x0000) {
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if (count++ >= PRD_ENTRIES)
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goto use_pio_instead;
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||||
*table++ = cpu_to_le32(0x8000);
|
||||
*table++ = cpu_to_le32(cur_addr + 0x8000);
|
||||
xcount = 0x8000;
|
||||
}
|
||||
*table++ = cpu_to_le32(xcount);
|
||||
cur_addr += bcount;
|
||||
cur_len -= bcount;
|
||||
}
|
||||
}
|
||||
|
||||
if (count) {
|
||||
if (!is_trm290)
|
||||
*--table |= cpu_to_le32(0x80000000);
|
||||
return count;
|
||||
}
|
||||
|
||||
use_pio_instead:
|
||||
printk(KERN_ERR "%s: %s\n", drive->name,
|
||||
count ? "DMA table too small" : "empty DMA table?");
|
||||
|
||||
ide_destroy_dmatable(drive);
|
||||
|
||||
return 0; /* revert to PIO for this request */
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_build_dmatable);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ide_destroy_dmatable - clean up DMA mapping
|
||||
* @drive: The drive to unmap
|
||||
|
|
@ -246,120 +161,6 @@ void ide_destroy_dmatable(ide_drive_t *drive)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
|
||||
/**
|
||||
* config_drive_for_dma - attempt to activate IDE DMA
|
||||
* @drive: the drive to place in DMA mode
|
||||
*
|
||||
* If the drive supports at least mode 2 DMA or UDMA of any kind
|
||||
* then attempt to place it into DMA mode. Drives that are known to
|
||||
* support DMA but predate the DMA properties or that are known
|
||||
* to have DMA handling bugs are also set up appropriately based
|
||||
* on the good/bad drive lists.
|
||||
*/
|
||||
|
||||
static int config_drive_for_dma(ide_drive_t *drive)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
u16 *id = drive->id;
|
||||
|
||||
if (drive->media != ide_disk) {
|
||||
if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable DMA on any drive that has
|
||||
* UltraDMA (mode 0/1/2/3/4/5/6) enabled
|
||||
*/
|
||||
if ((id[ATA_ID_FIELD_VALID] & 4) &&
|
||||
((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* Enable DMA on any drive that has mode2 DMA
|
||||
* (multi or single) enabled
|
||||
*/
|
||||
if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */
|
||||
if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||
|
||||
(id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
|
||||
return 1;
|
||||
|
||||
/* Consult the list of known "good" drives */
|
||||
if (ide_dma_good_drive(drive))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dma_timer_expiry - handle a DMA timeout
|
||||
* @drive: Drive that timed out
|
||||
*
|
||||
* An IDE DMA transfer timed out. In the event of an error we ask
|
||||
* the driver to resolve the problem, if a DMA transfer is still
|
||||
* in progress we continue to wait (arguably we need to add a
|
||||
* secondary 'I don't care what the drive thinks' timeout here)
|
||||
* Finally if we have an interrupt we let it complete the I/O.
|
||||
* But only one time - we clear expiry and if it's still not
|
||||
* completed after WAIT_CMD, we error and retry in PIO.
|
||||
* This can occur if an interrupt is lost or due to hang or bugs.
|
||||
*/
|
||||
|
||||
static int dma_timer_expiry(ide_drive_t *drive)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
|
||||
|
||||
printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
|
||||
drive->name, __func__, dma_stat);
|
||||
|
||||
if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
|
||||
return WAIT_CMD;
|
||||
|
||||
hwif->hwgroup->expiry = NULL; /* one free ride for now */
|
||||
|
||||
/* 1 dmaing, 2 error, 4 intr */
|
||||
if (dma_stat & 2) /* ERROR */
|
||||
return -1;
|
||||
|
||||
if (dma_stat & 1) /* DMAing */
|
||||
return WAIT_CMD;
|
||||
|
||||
if (dma_stat & 4) /* Got an Interrupt */
|
||||
return WAIT_CMD;
|
||||
|
||||
return 0; /* Status is unknown -- reset the bus */
|
||||
}
|
||||
|
||||
/**
|
||||
* ide_dma_host_set - Enable/disable DMA on a host
|
||||
* @drive: drive to control
|
||||
*
|
||||
* Enable/disable DMA on an IDE controller following generic
|
||||
* bus-mastering IDE controller behaviour.
|
||||
*/
|
||||
|
||||
void ide_dma_host_set(ide_drive_t *drive, int on)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
u8 unit = drive->dn & 1;
|
||||
u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
|
||||
|
||||
if (on)
|
||||
dma_stat |= (1 << (5 + unit));
|
||||
else
|
||||
dma_stat &= ~(1 << (5 + unit));
|
||||
|
||||
if (hwif->host_flags & IDE_HFLAG_MMIO)
|
||||
writeb(dma_stat,
|
||||
(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
|
||||
else
|
||||
outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_dma_host_set);
|
||||
#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
|
||||
|
||||
/**
|
||||
* ide_dma_off_quietly - Generic DMA kill
|
||||
* @drive: drive to control
|
||||
|
|
@ -406,154 +207,6 @@ void ide_dma_on(ide_drive_t *drive)
|
|||
drive->hwif->dma_ops->dma_host_set(drive, 1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
|
||||
/**
|
||||
* ide_dma_setup - begin a DMA phase
|
||||
* @drive: target device
|
||||
*
|
||||
* Build an IDE DMA PRD (IDE speak for scatter gather table)
|
||||
* and then set up the DMA transfer registers for a device
|
||||
* that follows generic IDE PCI DMA behaviour. Controllers can
|
||||
* override this function if they need to
|
||||
*
|
||||
* Returns 0 on success. If a PIO fallback is required then 1
|
||||
* is returned.
|
||||
*/
|
||||
|
||||
int ide_dma_setup(ide_drive_t *drive)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
struct request *rq = hwif->hwgroup->rq;
|
||||
unsigned int reading;
|
||||
u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
|
||||
u8 dma_stat;
|
||||
|
||||
if (rq_data_dir(rq))
|
||||
reading = 0;
|
||||
else
|
||||
reading = 1 << 3;
|
||||
|
||||
/* fall back to pio! */
|
||||
if (!ide_build_dmatable(drive, rq)) {
|
||||
ide_map_sg(drive, rq);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* PRD table */
|
||||
if (hwif->host_flags & IDE_HFLAG_MMIO)
|
||||
writel(hwif->dmatable_dma,
|
||||
(void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
|
||||
else
|
||||
outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
|
||||
|
||||
/* specify r/w */
|
||||
if (mmio)
|
||||
writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
||||
else
|
||||
outb(reading, hwif->dma_base + ATA_DMA_CMD);
|
||||
|
||||
/* read DMA status for INTR & ERROR flags */
|
||||
dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
|
||||
|
||||
/* clear INTR & ERROR flags */
|
||||
if (mmio)
|
||||
writeb(dma_stat | 6,
|
||||
(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
|
||||
else
|
||||
outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
|
||||
|
||||
drive->waiting_for_dma = 1;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_dma_setup);
|
||||
|
||||
void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
|
||||
{
|
||||
/* issue cmd to drive */
|
||||
ide_execute_command(drive, command, &ide_dma_intr, 2 * WAIT_CMD,
|
||||
dma_timer_expiry);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_dma_exec_cmd);
|
||||
|
||||
void ide_dma_start(ide_drive_t *drive)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
u8 dma_cmd;
|
||||
|
||||
/* Note that this is done *after* the cmd has
|
||||
* been issued to the drive, as per the BM-IDE spec.
|
||||
* The Promise Ultra33 doesn't work correctly when
|
||||
* we do this part before issuing the drive cmd.
|
||||
*/
|
||||
if (hwif->host_flags & IDE_HFLAG_MMIO) {
|
||||
dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
||||
/* start DMA */
|
||||
writeb(dma_cmd | 1,
|
||||
(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
||||
} else {
|
||||
dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
|
||||
outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD);
|
||||
}
|
||||
|
||||
wmb();
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_dma_start);
|
||||
|
||||
/* returns 1 on error, 0 otherwise */
|
||||
int ide_dma_end(ide_drive_t *drive)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
|
||||
u8 dma_stat = 0, dma_cmd = 0;
|
||||
|
||||
drive->waiting_for_dma = 0;
|
||||
|
||||
if (mmio) {
|
||||
/* get DMA command mode */
|
||||
dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
||||
/* stop DMA */
|
||||
writeb(dma_cmd & ~1,
|
||||
(void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
|
||||
} else {
|
||||
dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
|
||||
outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
|
||||
}
|
||||
|
||||
/* get DMA status */
|
||||
dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
|
||||
|
||||
if (mmio)
|
||||
/* clear the INTR & ERROR bits */
|
||||
writeb(dma_stat | 6,
|
||||
(void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
|
||||
else
|
||||
outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
|
||||
|
||||
/* purge DMA mappings */
|
||||
ide_destroy_dmatable(drive);
|
||||
/* verify good DMA status */
|
||||
wmb();
|
||||
return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_dma_end);
|
||||
|
||||
/* returns 1 if dma irq issued, 0 otherwise */
|
||||
int ide_dma_test_irq(ide_drive_t *drive)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
|
||||
|
||||
/* return 1 if INTR asserted */
|
||||
if ((dma_stat & 4) == 4)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_dma_test_irq);
|
||||
#else
|
||||
static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; }
|
||||
#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
|
||||
|
||||
int __ide_dma_bad_drive(ide_drive_t *drive)
|
||||
{
|
||||
u16 *id = drive->id;
|
||||
|
|
@ -846,17 +499,3 @@ int ide_allocate_dma_engine(ide_hwif_t *hwif)
|
|||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ide_allocate_dma_engine);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
|
||||
const struct ide_dma_ops sff_dma_ops = {
|
||||
.dma_host_set = ide_dma_host_set,
|
||||
.dma_setup = ide_dma_setup,
|
||||
.dma_exec_cmd = ide_dma_exec_cmd,
|
||||
.dma_start = ide_dma_start,
|
||||
.dma_end = ide_dma_end,
|
||||
.dma_test_irq = ide_dma_test_irq,
|
||||
.dma_timeout = ide_dma_timeout,
|
||||
.dma_lost_irq = ide_dma_lost_irq,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(sff_dma_ops);
|
||||
#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
|
||||
|
|
|
|||
|
|
@ -1412,6 +1412,7 @@ struct drive_list_entry {
|
|||
int ide_in_drive_list(u16 *, const struct drive_list_entry *);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDEDMA
|
||||
int ide_dma_good_drive(ide_drive_t *);
|
||||
int __ide_dma_bad_drive(ide_drive_t *);
|
||||
int ide_id_dma_bug(ide_drive_t *);
|
||||
|
||||
|
|
@ -1436,6 +1437,7 @@ int ide_build_sglist(ide_drive_t *, struct request *);
|
|||
void ide_destroy_dmatable(ide_drive_t *);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
|
||||
int config_drive_for_dma(ide_drive_t *);
|
||||
extern int ide_build_dmatable(ide_drive_t *, struct request *);
|
||||
void ide_dma_host_set(ide_drive_t *, int);
|
||||
extern int ide_dma_setup(ide_drive_t *);
|
||||
|
|
@ -1444,6 +1446,8 @@ extern void ide_dma_start(ide_drive_t *);
|
|||
int ide_dma_end(ide_drive_t *);
|
||||
int ide_dma_test_irq(ide_drive_t *);
|
||||
extern const struct ide_dma_ops sff_dma_ops;
|
||||
#else
|
||||
static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; }
|
||||
#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
|
||||
|
||||
void ide_dma_lost_irq(ide_drive_t *);
|
||||
|
|
|
|||
Loading…
Reference in a new issue