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crypto: aes-ni - Add support for more modes
Because kernel_fpu_begin() and kernel_fpu_end() operations are too slow, the performance gain of general mode implementation + aes-aesni is almost all compensated. The AES-NI support for more modes are implemented as follow: - Add a new AES algorithm implementation named __aes-aesni without kernel_fpu_begin/end() - Use fpu(<mode>(AES)) to provide kenrel_fpu_begin/end() invoking - Add <mode>(AES) ablkcipher, which uses cryptd(fpu(<mode>(AES))) to defer cryption to cryptd context in soft_irq context. Now the ctr, lrw, pcbc and xts support are added. Performance testing based on dm-crypt shows that cryption time can be reduced to 50% of general mode implementation + aes-aesni implementation. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Huang Ying
Herbert Xu
parent
150c7e8552
commit
2cf4ac8beb
2 changed files with 271 additions and 1 deletions
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@ -21,6 +21,22 @@
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#include <asm/i387.h>
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#include <asm/aes.h>
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#if defined(CONFIG_CRYPTO_CTR) || defined(CONFIG_CRYPTO_CTR_MODULE)
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#define HAS_CTR
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#endif
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#if defined(CONFIG_CRYPTO_LRW) || defined(CONFIG_CRYPTO_LRW_MODULE)
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#define HAS_LRW
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#endif
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#if defined(CONFIG_CRYPTO_PCBC) || defined(CONFIG_CRYPTO_PCBC_MODULE)
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#define HAS_PCBC
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#endif
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#if defined(CONFIG_CRYPTO_XTS) || defined(CONFIG_CRYPTO_XTS_MODULE)
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#define HAS_XTS
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#endif
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struct async_aes_ctx {
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struct cryptd_ablkcipher *cryptd_tfm;
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};
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@ -137,6 +153,41 @@ static struct crypto_alg aesni_alg = {
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}
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};
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static void __aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
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{
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struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
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aesni_enc(ctx, dst, src);
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}
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static void __aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
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{
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struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
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aesni_dec(ctx, dst, src);
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}
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static struct crypto_alg __aesni_alg = {
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.cra_name = "__aes-aesni",
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.cra_driver_name = "__driver-aes-aesni",
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.cra_priority = 0,
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.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
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.cra_alignmask = 0,
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.cra_module = THIS_MODULE,
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.cra_list = LIST_HEAD_INIT(__aesni_alg.cra_list),
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.cra_u = {
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.cipher = {
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.cia_min_keysize = AES_MIN_KEY_SIZE,
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.cia_max_keysize = AES_MAX_KEY_SIZE,
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.cia_setkey = aes_set_key,
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.cia_encrypt = __aes_encrypt,
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.cia_decrypt = __aes_decrypt
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}
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}
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};
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static int ecb_encrypt(struct blkcipher_desc *desc,
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struct scatterlist *dst, struct scatterlist *src,
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unsigned int nbytes)
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@ -277,8 +328,16 @@ static int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
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unsigned int key_len)
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{
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struct async_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
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struct crypto_ablkcipher *child = &ctx->cryptd_tfm->base;
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int err;
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return crypto_ablkcipher_setkey(&ctx->cryptd_tfm->base, key, key_len);
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crypto_ablkcipher_clear_flags(child, CRYPTO_TFM_REQ_MASK);
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crypto_ablkcipher_set_flags(child, crypto_ablkcipher_get_flags(tfm)
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& CRYPTO_TFM_REQ_MASK);
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err = crypto_ablkcipher_setkey(child, key, key_len);
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crypto_ablkcipher_set_flags(tfm, crypto_ablkcipher_get_flags(child)
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& CRYPTO_TFM_RES_MASK);
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return err;
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}
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static int ablk_encrypt(struct ablkcipher_request *req)
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@ -411,6 +470,163 @@ static struct crypto_alg ablk_cbc_alg = {
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},
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};
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#ifdef HAS_CTR
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static int ablk_ctr_init(struct crypto_tfm *tfm)
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{
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struct cryptd_ablkcipher *cryptd_tfm;
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cryptd_tfm = cryptd_alloc_ablkcipher("fpu(ctr(__driver-aes-aesni))",
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0, 0);
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if (IS_ERR(cryptd_tfm))
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return PTR_ERR(cryptd_tfm);
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ablk_init_common(tfm, cryptd_tfm);
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return 0;
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}
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static struct crypto_alg ablk_ctr_alg = {
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.cra_name = "ctr(aes)",
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.cra_driver_name = "ctr-aes-aesni",
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.cra_priority = 400,
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.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
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.cra_blocksize = 1,
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.cra_ctxsize = sizeof(struct async_aes_ctx),
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.cra_alignmask = 0,
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.cra_type = &crypto_ablkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_list = LIST_HEAD_INIT(ablk_ctr_alg.cra_list),
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.cra_init = ablk_ctr_init,
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.cra_exit = ablk_exit,
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.cra_u = {
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.ablkcipher = {
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.setkey = ablk_set_key,
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.encrypt = ablk_encrypt,
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.decrypt = ablk_decrypt,
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.geniv = "chainiv",
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},
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},
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};
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#endif
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#ifdef HAS_LRW
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static int ablk_lrw_init(struct crypto_tfm *tfm)
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{
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struct cryptd_ablkcipher *cryptd_tfm;
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cryptd_tfm = cryptd_alloc_ablkcipher("fpu(lrw(__driver-aes-aesni))",
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0, 0);
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if (IS_ERR(cryptd_tfm))
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return PTR_ERR(cryptd_tfm);
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ablk_init_common(tfm, cryptd_tfm);
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return 0;
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}
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static struct crypto_alg ablk_lrw_alg = {
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.cra_name = "lrw(aes)",
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.cra_driver_name = "lrw-aes-aesni",
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.cra_priority = 400,
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.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct async_aes_ctx),
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.cra_alignmask = 0,
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.cra_type = &crypto_ablkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_list = LIST_HEAD_INIT(ablk_lrw_alg.cra_list),
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.cra_init = ablk_lrw_init,
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.cra_exit = ablk_exit,
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.cra_u = {
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.ablkcipher = {
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.min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.setkey = ablk_set_key,
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.encrypt = ablk_encrypt,
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.decrypt = ablk_decrypt,
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},
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},
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};
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#endif
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#ifdef HAS_PCBC
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static int ablk_pcbc_init(struct crypto_tfm *tfm)
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{
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struct cryptd_ablkcipher *cryptd_tfm;
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cryptd_tfm = cryptd_alloc_ablkcipher("fpu(pcbc(__driver-aes-aesni))",
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0, 0);
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if (IS_ERR(cryptd_tfm))
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return PTR_ERR(cryptd_tfm);
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ablk_init_common(tfm, cryptd_tfm);
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return 0;
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}
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static struct crypto_alg ablk_pcbc_alg = {
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.cra_name = "pcbc(aes)",
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.cra_driver_name = "pcbc-aes-aesni",
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.cra_priority = 400,
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.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct async_aes_ctx),
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.cra_alignmask = 0,
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.cra_type = &crypto_ablkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_list = LIST_HEAD_INIT(ablk_pcbc_alg.cra_list),
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.cra_init = ablk_pcbc_init,
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.cra_exit = ablk_exit,
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.cra_u = {
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.ablkcipher = {
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.setkey = ablk_set_key,
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.encrypt = ablk_encrypt,
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.decrypt = ablk_decrypt,
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},
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},
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};
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#endif
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#ifdef HAS_XTS
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static int ablk_xts_init(struct crypto_tfm *tfm)
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{
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struct cryptd_ablkcipher *cryptd_tfm;
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cryptd_tfm = cryptd_alloc_ablkcipher("fpu(xts(__driver-aes-aesni))",
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0, 0);
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if (IS_ERR(cryptd_tfm))
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return PTR_ERR(cryptd_tfm);
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ablk_init_common(tfm, cryptd_tfm);
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return 0;
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}
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static struct crypto_alg ablk_xts_alg = {
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.cra_name = "xts(aes)",
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.cra_driver_name = "xts-aes-aesni",
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.cra_priority = 400,
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.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct async_aes_ctx),
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.cra_alignmask = 0,
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.cra_type = &crypto_ablkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_list = LIST_HEAD_INIT(ablk_xts_alg.cra_list),
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.cra_init = ablk_xts_init,
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.cra_exit = ablk_exit,
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.cra_u = {
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.ablkcipher = {
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.min_keysize = 2 * AES_MIN_KEY_SIZE,
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.max_keysize = 2 * AES_MAX_KEY_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.setkey = ablk_set_key,
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.encrypt = ablk_encrypt,
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.decrypt = ablk_decrypt,
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},
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},
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};
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#endif
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static int __init aesni_init(void)
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{
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int err;
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@ -421,6 +637,8 @@ static int __init aesni_init(void)
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}
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if ((err = crypto_register_alg(&aesni_alg)))
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goto aes_err;
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if ((err = crypto_register_alg(&__aesni_alg)))
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goto __aes_err;
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if ((err = crypto_register_alg(&blk_ecb_alg)))
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goto blk_ecb_err;
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if ((err = crypto_register_alg(&blk_cbc_alg)))
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@ -429,9 +647,41 @@ static int __init aesni_init(void)
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goto ablk_ecb_err;
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if ((err = crypto_register_alg(&ablk_cbc_alg)))
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goto ablk_cbc_err;
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#ifdef HAS_CTR
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if ((err = crypto_register_alg(&ablk_ctr_alg)))
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goto ablk_ctr_err;
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#endif
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#ifdef HAS_LRW
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if ((err = crypto_register_alg(&ablk_lrw_alg)))
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goto ablk_lrw_err;
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#endif
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#ifdef HAS_PCBC
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if ((err = crypto_register_alg(&ablk_pcbc_alg)))
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goto ablk_pcbc_err;
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#endif
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#ifdef HAS_XTS
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if ((err = crypto_register_alg(&ablk_xts_alg)))
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goto ablk_xts_err;
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#endif
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return err;
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#ifdef HAS_XTS
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ablk_xts_err:
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#endif
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#ifdef HAS_PCBC
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crypto_unregister_alg(&ablk_pcbc_alg);
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ablk_pcbc_err:
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#endif
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#ifdef HAS_LRW
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crypto_unregister_alg(&ablk_lrw_alg);
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ablk_lrw_err:
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#endif
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#ifdef HAS_CTR
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crypto_unregister_alg(&ablk_ctr_alg);
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ablk_ctr_err:
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#endif
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crypto_unregister_alg(&ablk_cbc_alg);
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ablk_cbc_err:
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crypto_unregister_alg(&ablk_ecb_alg);
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ablk_ecb_err:
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@ -439,6 +689,8 @@ ablk_ecb_err:
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blk_cbc_err:
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crypto_unregister_alg(&blk_ecb_alg);
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blk_ecb_err:
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crypto_unregister_alg(&__aesni_alg);
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__aes_err:
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crypto_unregister_alg(&aesni_alg);
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aes_err:
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return err;
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@ -446,10 +698,23 @@ aes_err:
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static void __exit aesni_exit(void)
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{
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#ifdef HAS_XTS
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crypto_unregister_alg(&ablk_xts_alg);
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#endif
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#ifdef HAS_PCBC
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crypto_unregister_alg(&ablk_pcbc_alg);
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#endif
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#ifdef HAS_LRW
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crypto_unregister_alg(&ablk_lrw_alg);
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#endif
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#ifdef HAS_CTR
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crypto_unregister_alg(&ablk_ctr_alg);
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#endif
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crypto_unregister_alg(&ablk_cbc_alg);
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crypto_unregister_alg(&ablk_ecb_alg);
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crypto_unregister_alg(&blk_cbc_alg);
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crypto_unregister_alg(&blk_ecb_alg);
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crypto_unregister_alg(&__aesni_alg);
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crypto_unregister_alg(&aesni_alg);
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}
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@ -491,6 +491,7 @@ config CRYPTO_AES_NI_INTEL
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select CRYPTO_AES_X86_64
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select CRYPTO_CRYPTD
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select CRYPTO_ALGAPI
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select CRYPTO_FPU
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help
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Use Intel AES-NI instructions for AES algorithm.
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@ -510,6 +511,10 @@ config CRYPTO_AES_NI_INTEL
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See <http://csrc.nist.gov/encryption/aes/> for more information.
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In addition to AES cipher algorithm support, the
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acceleration for some popular block cipher mode is supported
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too, including ECB, CBC, CTR, LRW, PCBC, XTS.
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config CRYPTO_ANUBIS
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tristate "Anubis cipher algorithm"
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select CRYPTO_ALGAPI
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