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V4L/DVB (12899): DiB0070: Indenting driver with indent -linux
In order to follow a little bit the kernel coding style from now on after the generation of that driver file and indent -linux call is emitted. Signed-off-by: Patrick Boettcher <pboettcher@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Patrick Boettcher
Mauro Carvalho Chehab
parent
7e5ce6515d
commit
2a6a30e05c
2 changed files with 417 additions and 406 deletions
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@ -50,16 +50,16 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
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#define DIB0070S_P1A 0x02
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enum frontend_tune_state {
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CT_TUNER_START = 10,
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CT_TUNER_STEP_0,
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CT_TUNER_STEP_1,
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CT_TUNER_STEP_2,
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CT_TUNER_STEP_3,
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CT_TUNER_STEP_4,
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CT_TUNER_STEP_5,
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CT_TUNER_STEP_6,
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CT_TUNER_STEP_7,
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CT_TUNER_STOP,
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CT_TUNER_START = 10,
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CT_TUNER_STEP_0,
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CT_TUNER_STEP_1,
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CT_TUNER_STEP_2,
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CT_TUNER_STEP_3,
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CT_TUNER_STEP_4,
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CT_TUNER_STEP_5,
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CT_TUNER_STEP_6,
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CT_TUNER_STEP_7,
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CT_TUNER_STOP,
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};
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#define FE_CALLBACK_TIME_NEVER 0xffffffff
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@ -71,10 +71,10 @@ struct dib0070_state {
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u16 wbd_ff_offset;
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u8 revision;
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enum frontend_tune_state tune_state;
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u32 current_rf;
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enum frontend_tune_state tune_state;
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u32 current_rf;
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/* for the captrim binary search */
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/* for the captrim binary search */
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s8 step;
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u16 adc_diff;
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@ -85,7 +85,7 @@ struct dib0070_state {
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const struct dib0070_tuning *current_tune_table_index;
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const struct dib0070_lna_match *lna_match;
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u8 wbd_gain_current;
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u8 wbd_gain_current;
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u16 wbd_offset_3_3[2];
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};
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@ -93,8 +93,8 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
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{
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u8 b[2];
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struct i2c_msg msg[2] = {
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{ .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
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{ .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2 },
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{.addr = state->cfg->i2c_address,.flags = 0,.buf = ®,.len = 1},
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{.addr = state->cfg->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
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};
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if (i2c_transfer(state->i2c, msg, 2) != 2) {
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printk(KERN_WARNING "DiB0070 I2C read failed\n");
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@ -106,7 +106,7 @@ static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
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static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
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{
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u8 b[3] = { reg, val >> 8, val & 0xff };
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struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 };
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struct i2c_msg msg = {.addr = state->cfg->i2c_address,.flags = 0,.buf = b,.len = 3 };
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if (i2c_transfer(state->i2c, &msg, 1) != 1) {
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printk(KERN_WARNING "DiB0070 I2C write failed\n");
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return -EREMOTEIO;
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@ -124,34 +124,34 @@ static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
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static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
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{
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struct dib0070_state *st = fe->tuner_priv;
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u16 tmp = dib0070_read_reg(st, 0x02) & 0x3fff;
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struct dib0070_state *state = fe->tuner_priv;
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u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
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if (fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
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tmp |= (0 << 14);
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else if (fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
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tmp |= (1 << 14);
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else if (fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
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tmp |= (2 << 14);
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else
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tmp |= (3 << 14);
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if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 7000)
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tmp |= (0 << 14);
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else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 6000)
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tmp |= (1 << 14);
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else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 > 5000)
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tmp |= (2 << 14);
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else
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tmp |= (3 << 14);
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dib0070_write_reg(st, 0x02, tmp);
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dib0070_write_reg(state, 0x02, tmp);
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/* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
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if (fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
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u16 value = dib0070_read_reg(st, 0x17);
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/* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
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if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
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u16 value = dib0070_read_reg(state, 0x17);
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dib0070_write_reg(st, 0x17, value & 0xfffc);
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tmp = dib0070_read_reg(st, 0x01) & 0x01ff;
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dib0070_write_reg(st, 0x01, tmp | (60 << 9));
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dib0070_write_reg(state, 0x17, value & 0xfffc);
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tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
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dib0070_write_reg(state, 0x01, tmp | (60 << 9));
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dib0070_write_reg(st, 0x17, value);
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}
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dib0070_write_reg(state, 0x17, value);
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}
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return 0;
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}
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static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *tune_state)
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static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state)
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{
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int8_t step_sign;
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u16 adc;
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@ -159,26 +159,26 @@ static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *t
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if (*tune_state == CT_TUNER_STEP_0) {
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dib0070_write_reg(st, 0x0f, 0xed10);
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dib0070_write_reg(st, 0x17, 0x0034);
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dib0070_write_reg(state, 0x0f, 0xed10);
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dib0070_write_reg(state, 0x17, 0x0034);
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dib0070_write_reg(st, 0x18, 0x0032);
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st->step = st->captrim = st->fcaptrim = 64;
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st->adc_diff = 3000;
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dib0070_write_reg(state, 0x18, 0x0032);
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state->step = state->captrim = state->fcaptrim = 64;
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state->adc_diff = 3000;
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ret = 20;
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*tune_state = CT_TUNER_STEP_1;
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*tune_state = CT_TUNER_STEP_1;
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} else if (*tune_state == CT_TUNER_STEP_1) {
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st->step /= 2;
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dib0070_write_reg(st, 0x14, st->lo4 | st->captrim);
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state->step /= 2;
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dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
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ret = 15;
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*tune_state = CT_TUNER_STEP_2;
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} else if (*tune_state == CT_TUNER_STEP_2) {
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adc = dib0070_read_reg(st, 0x19);
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adc = dib0070_read_reg(state, 0x19);
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dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", st->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
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dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc * (u32) 1800 / (u32) 1024);
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if (adc >= 400) {
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adc -= 400;
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@ -188,24 +188,22 @@ static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *t
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step_sign = 1;
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}
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if (adc < st->adc_diff) {
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dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", st->captrim, adc, st->adc_diff);
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st->adc_diff = adc;
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st->fcaptrim = st->captrim;
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if (adc < state->adc_diff) {
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dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff);
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state->adc_diff = adc;
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state->fcaptrim = state->captrim;
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}
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st->captrim += (step_sign * st->step);
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state->captrim += (step_sign * state->step);
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if (st->step >= 1)
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if (state->step >= 1)
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*tune_state = CT_TUNER_STEP_1;
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else
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*tune_state = CT_TUNER_STEP_3;
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} else if (*tune_state == CT_TUNER_STEP_3) {
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dib0070_write_reg(st, 0x14, st->lo4 | st->fcaptrim);
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dib0070_write_reg(st, 0x18, 0x07ff);
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dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
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dib0070_write_reg(state, 0x18, 0x07ff);
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*tune_state = CT_TUNER_STEP_4;
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}
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@ -215,374 +213,391 @@ static int dib0070_captrim(struct dib0070_state *st, enum frontend_tune_state *t
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static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
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{
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struct dib0070_state *state = fe->tuner_priv;
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u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
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dprintk( "CTRL_LO5: 0x%x", lo5);
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u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
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dprintk("CTRL_LO5: 0x%x", lo5);
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return dib0070_write_reg(state, 0x15, lo5);
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}
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struct dib0070_tuning
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void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
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{
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u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
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u8 switch_trim;
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u8 vco_band;
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u8 hfdiv;
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u8 vco_multi;
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u8 presc;
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u8 wbdmux;
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u16 tuner_enable;
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};
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struct dib0070_state *state = fe->tuner_priv;
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struct dib0070_lna_match
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{
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u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
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u8 lna_band;
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};
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static const struct dib0070_tuning dib0070s_tuning_table[] =
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{
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{ 570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */
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{ 700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 },
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{ 863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 },
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{ 1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */
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{ 1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
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{ 2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
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{ 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */
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};
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static const struct dib0070_tuning dib0070_tuning_table[] =
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{
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{ 115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
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{ 179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
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{ 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
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{ 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
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{ 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
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{ 699999, 2, 0 ,1, 4, 2, 2, 0x4000 | 0x0800 },
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{ 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
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{ 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
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};
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static const struct dib0070_lna_match dib0070_lna_flip_chip[] =
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{
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{ 180000, 0 }, /* VHF */
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{ 188000, 1 },
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{ 196400, 2 },
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{ 250000, 3 },
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{ 550000, 0 }, /* UHF */
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{ 590000, 1 },
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{ 666000, 3 },
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{ 864000, 5 },
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{ 1500000, 0 }, /* LBAND or everything higher than UHF */
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{ 1600000, 1 },
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{ 2000000, 3 },
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{ 0xffffffff, 7 },
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};
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static const struct dib0070_lna_match dib0070_lna[] =
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{
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{ 180000, 0 }, /* VHF */
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{ 188000, 1 },
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{ 196400, 2 },
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{ 250000, 3 },
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{ 550000, 2 }, /* UHF */
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{ 650000, 3 },
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{ 750000, 5 },
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{ 850000, 6 },
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{ 864000, 7 },
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{ 1500000, 0 }, /* LBAND or everything higher than UHF */
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{ 1600000, 1 },
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{ 2000000, 3 },
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{ 0xffffffff, 7 },
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};
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#define LPF 100 // define for the loop filter 100kHz by default 16-07-06
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static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
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{
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struct dib0070_state *st = fe->tuner_priv;
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const struct dib0070_tuning *tune;
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const struct dib0070_lna_match *lna_match;
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enum frontend_tune_state *tune_state = &st->tune_state;
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int ret = 10; /* 1ms is the default delay most of the time */
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u8 band = (u8)BAND_OF_FREQUENCY(ch->frequency/1000);
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u32 freq = ch->frequency/1000 + (band == BAND_VHF ? st->cfg->freq_offset_khz_vhf : st->cfg->freq_offset_khz_uhf);
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#ifdef CONFIG_STANDARD_ISDBT
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if (fe->dtv_property_cache.delivery_system == SYS_ISDBT && ch->u.isdbt.sb_mode == 1)
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if ( ( (ch->u.isdbt.sb_conn_total_seg % 2) && (ch->u.isdbt.sb_wanted_seg == ((ch->u.isdbt.sb_conn_total_seg/2) + 1) ) ) ||
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( ( (ch->u.isdbt.sb_conn_total_seg % 2) == 0) && (ch->u.isdbt.sb_wanted_seg == (ch->u.isdbt.sb_conn_total_seg/2) ) ) ||
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( ( (ch->u.isdbt.sb_conn_total_seg % 2) == 0) && (ch->u.isdbt.sb_wanted_seg == ((ch->u.isdbt.sb_conn_total_seg/2)+1))) )
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freq += 850;
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#endif
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if (st->current_rf != freq) {
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switch (st->revision) {
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case DIB0070S_P1A:
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tune = dib0070s_tuning_table;
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lna_match = dib0070_lna;
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break;
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default:
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tune = dib0070_tuning_table;
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if (st->cfg->flip_chip)
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lna_match = dib0070_lna_flip_chip;
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else
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lna_match = dib0070_lna;
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break;
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}
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while (freq > tune->max_freq) /* find the right one */
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tune++;
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while (freq > lna_match->max_freq) /* find the right one */
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lna_match++;
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st->current_tune_table_index = tune;
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st->lna_match = lna_match;
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}
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if (*tune_state == CT_TUNER_START) {
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dprintk( "Tuning for Band: %hd (%d kHz)", band, freq);
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if (st->current_rf != freq) {
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u8 REFDIV;
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u32 FBDiv, Rest, FREF, VCOF_kHz;
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u8 Den;
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st->current_rf = freq;
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st->lo4 = (st->current_tune_table_index->vco_band << 11) | (st->current_tune_table_index->hfdiv << 7);
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dib0070_write_reg(st, 0x17, 0x30);
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VCOF_kHz = st->current_tune_table_index->vco_multi * freq * 2;
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switch (band) {
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case BAND_VHF:
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REFDIV = (u8) ((st->cfg->clock_khz + 9999) / 10000);
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break;
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case BAND_FM:
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REFDIV = (u8) ((st->cfg->clock_khz) / 1000);
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break;
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default:
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REFDIV = (u8) ( st->cfg->clock_khz / 10000);
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break;
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}
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FREF = st->cfg->clock_khz / REFDIV;
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switch (st->revision) {
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case DIB0070S_P1A:
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FBDiv = (VCOF_kHz / st->current_tune_table_index->presc / FREF);
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Rest = (VCOF_kHz / st->current_tune_table_index->presc) - FBDiv * FREF;
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break;
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case DIB0070_P1G:
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case DIB0070_P1F:
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default:
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FBDiv = (freq / (FREF / 2));
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Rest = 2 * freq - FBDiv * FREF;
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break;
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}
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||||
|
||||
|
||||
if (Rest < LPF) Rest = 0;
|
||||
else if (Rest < 2 * LPF) Rest = 2 * LPF;
|
||||
else if (Rest > (FREF - LPF)) { Rest = 0 ; FBDiv += 1; }
|
||||
else if (Rest > (FREF - 2 * LPF)) Rest = FREF - 2 * LPF;
|
||||
Rest = (Rest * 6528) / (FREF / 10);
|
||||
|
||||
Den = 1;
|
||||
if (Rest > 0) {
|
||||
st->lo4 |= (1 << 14) | (1 << 12);
|
||||
Den = 255;
|
||||
}
|
||||
|
||||
|
||||
dib0070_write_reg(st, 0x11, (u16)FBDiv);
|
||||
dib0070_write_reg(st, 0x12, (Den << 8) | REFDIV);
|
||||
dib0070_write_reg(st, 0x13, (u16) Rest);
|
||||
|
||||
if (st->revision == DIB0070S_P1A) {
|
||||
|
||||
if (band == BAND_SBAND) {
|
||||
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
|
||||
dib0070_write_reg(st, 0x1d,0xFFFF);
|
||||
} else
|
||||
dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
|
||||
}
|
||||
|
||||
|
||||
dib0070_write_reg(st, 0x20, 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | st->current_tune_table_index->tuner_enable);
|
||||
|
||||
dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF);
|
||||
dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest);
|
||||
dprintk( "Num: %hd, Den: %hd, SD: %hd",(u16) Rest, Den, (st->lo4 >> 12) & 0x1);
|
||||
dprintk( "HFDIV code: %hd", st->current_tune_table_index->hfdiv);
|
||||
dprintk( "VCO = %hd", st->current_tune_table_index->vco_band);
|
||||
dprintk( "VCOF: ((%hd*%d) << 1))", st->current_tune_table_index->vco_multi, freq);
|
||||
|
||||
*tune_state = CT_TUNER_STEP_0;
|
||||
} else { /* we are already tuned to this frequency - the configuration is correct */
|
||||
ret = 50; /* wakeup time */
|
||||
*tune_state = CT_TUNER_STEP_5;
|
||||
}
|
||||
} else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
|
||||
|
||||
ret = dib0070_captrim(st, tune_state);
|
||||
|
||||
} else if (*tune_state == CT_TUNER_STEP_4) {
|
||||
const struct dib0070_wbd_gain_cfg *tmp = st->cfg->wbd_gain;
|
||||
if (tmp != NULL) {
|
||||
while (freq/1000 > tmp->freq) /* find the right one */
|
||||
tmp++;
|
||||
dib0070_write_reg(st, 0x0f, (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (st->current_tune_table_index->wbdmux << 0));
|
||||
st->wbd_gain_current = tmp->wbd_gain_val;
|
||||
if (open) {
|
||||
dib0070_write_reg(state, 0x1b, 0xff00);
|
||||
dib0070_write_reg(state, 0x1a, 0x0000);
|
||||
} else {
|
||||
dib0070_write_reg(st, 0x0f, (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (st->current_tune_table_index->wbdmux << 0));
|
||||
st->wbd_gain_current = 6;
|
||||
dib0070_write_reg(state, 0x1b, 0x4112);
|
||||
if (state->cfg->vga_filter != 0) {
|
||||
dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
|
||||
dprintk("vga filter register is set to %x", state->cfg->vga_filter);
|
||||
} else
|
||||
dib0070_write_reg(state, 0x1a, 0x0009);
|
||||
}
|
||||
|
||||
dib0070_write_reg(st, 0x06, 0x3fff);
|
||||
dib0070_write_reg(st, 0x07, (st->current_tune_table_index->switch_trim << 11) | (7 << 8) | (st->lna_match->lna_band << 3) | (3 << 0));
|
||||
dib0070_write_reg(st, 0x08, (st->lna_match->lna_band << 10) | (3 << 7) | (127));
|
||||
dib0070_write_reg(st, 0x0d, 0x0d80);
|
||||
|
||||
|
||||
dib0070_write_reg(st, 0x18, 0x07ff);
|
||||
dib0070_write_reg(st, 0x17, 0x0033);
|
||||
|
||||
|
||||
*tune_state = CT_TUNER_STEP_5;
|
||||
} else if (*tune_state == CT_TUNER_STEP_5) {
|
||||
dib0070_set_bandwidth(fe, ch);
|
||||
*tune_state = CT_TUNER_STOP;
|
||||
} else {
|
||||
ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
|
||||
struct dib0070_tuning {
|
||||
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
|
||||
u8 switch_trim;
|
||||
u8 vco_band;
|
||||
u8 hfdiv;
|
||||
u8 vco_multi;
|
||||
u8 presc;
|
||||
u8 wbdmux;
|
||||
u16 tuner_enable;
|
||||
};
|
||||
|
||||
struct dib0070_lna_match {
|
||||
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
|
||||
u8 lna_band;
|
||||
};
|
||||
|
||||
static const struct dib0070_tuning dib0070s_tuning_table[] = {
|
||||
{570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800}, /* UHF */
|
||||
{700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800},
|
||||
{863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800},
|
||||
{1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400}, /* LBAND */
|
||||
{1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
|
||||
{2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400},
|
||||
{0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000}, /* SBAND */
|
||||
};
|
||||
|
||||
static const struct dib0070_tuning dib0070_tuning_table[] = {
|
||||
{115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000}, /* FM below 92MHz cannot be tuned */
|
||||
{179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000}, /* VHF */
|
||||
{189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000},
|
||||
{250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000},
|
||||
{569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800}, /* UHF */
|
||||
{699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800},
|
||||
{863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800},
|
||||
{0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400}, /* LBAND or everything higher than UHF */
|
||||
};
|
||||
|
||||
static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
|
||||
{180000, 0}, /* VHF */
|
||||
{188000, 1},
|
||||
{196400, 2},
|
||||
{250000, 3},
|
||||
{550000, 0}, /* UHF */
|
||||
{590000, 1},
|
||||
{666000, 3},
|
||||
{864000, 5},
|
||||
{1500000, 0}, /* LBAND or everything higher than UHF */
|
||||
{1600000, 1},
|
||||
{2000000, 3},
|
||||
{0xffffffff, 7},
|
||||
};
|
||||
|
||||
static const struct dib0070_lna_match dib0070_lna[] = {
|
||||
{180000, 0}, /* VHF */
|
||||
{188000, 1},
|
||||
{196400, 2},
|
||||
{250000, 3},
|
||||
{550000, 2}, /* UHF */
|
||||
{650000, 3},
|
||||
{750000, 5},
|
||||
{850000, 6},
|
||||
{864000, 7},
|
||||
{1500000, 0}, /* LBAND or everything higher than UHF */
|
||||
{1600000, 1},
|
||||
{2000000, 3},
|
||||
{0xffffffff, 7},
|
||||
};
|
||||
|
||||
#define LPF 100 // define for the loop filter 100kHz by default 16-07-06
|
||||
static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
|
||||
{
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
|
||||
const struct dib0070_tuning *tune;
|
||||
const struct dib0070_lna_match *lna_match;
|
||||
|
||||
enum frontend_tune_state *tune_state = &state->tune_state;
|
||||
int ret = 10; /* 1ms is the default delay most of the time */
|
||||
|
||||
u8 band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
|
||||
u32 freq = fe->dtv_property_cache.frequency / 1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
|
||||
|
||||
#ifdef CONFIG_SYS_ISDBT
|
||||
if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
|
||||
if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
|
||||
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
|
||||
|| (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
|
||||
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
|
||||
|| (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
|
||||
&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
|
||||
freq += 850;
|
||||
#endif
|
||||
if (state->current_rf != freq) {
|
||||
|
||||
switch (state->revision) {
|
||||
case DIB0070S_P1A:
|
||||
tune = dib0070s_tuning_table;
|
||||
lna_match = dib0070_lna;
|
||||
break;
|
||||
default:
|
||||
tune = dib0070_tuning_table;
|
||||
if (state->cfg->flip_chip)
|
||||
lna_match = dib0070_lna_flip_chip;
|
||||
else
|
||||
lna_match = dib0070_lna;
|
||||
break;
|
||||
}
|
||||
while (freq > tune->max_freq) /* find the right one */
|
||||
tune++;
|
||||
while (freq > lna_match->max_freq) /* find the right one */
|
||||
lna_match++;
|
||||
|
||||
state->current_tune_table_index = tune;
|
||||
state->lna_match = lna_match;
|
||||
}
|
||||
|
||||
if (*tune_state == CT_TUNER_START) {
|
||||
dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
|
||||
if (state->current_rf != freq) {
|
||||
u8 REFDIV;
|
||||
u32 FBDiv, Rest, FREF, VCOF_kHz;
|
||||
u8 Den;
|
||||
|
||||
state->current_rf = freq;
|
||||
state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
|
||||
|
||||
dib0070_write_reg(state, 0x17, 0x30);
|
||||
|
||||
VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
|
||||
|
||||
switch (band) {
|
||||
case BAND_VHF:
|
||||
REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
|
||||
break;
|
||||
case BAND_FM:
|
||||
REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
|
||||
break;
|
||||
default:
|
||||
REFDIV = (u8) (state->cfg->clock_khz / 10000);
|
||||
break;
|
||||
}
|
||||
FREF = state->cfg->clock_khz / REFDIV;
|
||||
|
||||
switch (state->revision) {
|
||||
case DIB0070S_P1A:
|
||||
FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
|
||||
Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
|
||||
break;
|
||||
|
||||
case DIB0070_P1G:
|
||||
case DIB0070_P1F:
|
||||
default:
|
||||
FBDiv = (freq / (FREF / 2));
|
||||
Rest = 2 * freq - FBDiv * FREF;
|
||||
break;
|
||||
}
|
||||
|
||||
if (Rest < LPF)
|
||||
Rest = 0;
|
||||
else if (Rest < 2 * LPF)
|
||||
Rest = 2 * LPF;
|
||||
else if (Rest > (FREF - LPF)) {
|
||||
Rest = 0;
|
||||
FBDiv += 1;
|
||||
} else if (Rest > (FREF - 2 * LPF))
|
||||
Rest = FREF - 2 * LPF;
|
||||
Rest = (Rest * 6528) / (FREF / 10);
|
||||
|
||||
Den = 1;
|
||||
if (Rest > 0) {
|
||||
state->lo4 |= (1 << 14) | (1 << 12);
|
||||
Den = 255;
|
||||
}
|
||||
|
||||
dib0070_write_reg(state, 0x11, (u16) FBDiv);
|
||||
dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
|
||||
dib0070_write_reg(state, 0x13, (u16) Rest);
|
||||
|
||||
if (state->revision == DIB0070S_P1A) {
|
||||
|
||||
if (band == BAND_SBAND) {
|
||||
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
|
||||
dib0070_write_reg(state, 0x1d, 0xFFFF);
|
||||
} else
|
||||
dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
|
||||
}
|
||||
|
||||
dib0070_write_reg(state, 0x20,
|
||||
0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
|
||||
|
||||
dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
|
||||
dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
|
||||
dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
|
||||
dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
|
||||
dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
|
||||
dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
|
||||
|
||||
*tune_state = CT_TUNER_STEP_0;
|
||||
} else { /* we are already tuned to this frequency - the configuration is correct */
|
||||
ret = 50; /* wakeup time */
|
||||
*tune_state = CT_TUNER_STEP_5;
|
||||
}
|
||||
} else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
|
||||
|
||||
ret = dib0070_captrim(state, tune_state);
|
||||
|
||||
} else if (*tune_state == CT_TUNER_STEP_4) {
|
||||
const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
|
||||
if (tmp != NULL) {
|
||||
while (freq / 1000 > tmp->freq) /* find the right one */
|
||||
tmp++;
|
||||
dib0070_write_reg(state, 0x0f,
|
||||
(0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state->
|
||||
current_tune_table_index->
|
||||
wbdmux << 0));
|
||||
state->wbd_gain_current = tmp->wbd_gain_val;
|
||||
} else {
|
||||
dib0070_write_reg(state, 0x0f,
|
||||
(0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index->
|
||||
wbdmux << 0));
|
||||
state->wbd_gain_current = 6;
|
||||
}
|
||||
|
||||
dib0070_write_reg(state, 0x06, 0x3fff);
|
||||
dib0070_write_reg(state, 0x07,
|
||||
(state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
|
||||
dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
|
||||
dib0070_write_reg(state, 0x0d, 0x0d80);
|
||||
|
||||
dib0070_write_reg(state, 0x18, 0x07ff);
|
||||
dib0070_write_reg(state, 0x17, 0x0033);
|
||||
|
||||
*tune_state = CT_TUNER_STEP_5;
|
||||
} else if (*tune_state == CT_TUNER_STEP_5) {
|
||||
dib0070_set_bandwidth(fe, ch);
|
||||
*tune_state = CT_TUNER_STOP;
|
||||
} else {
|
||||
ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
|
||||
{
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
uint32_t ret;
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
uint32_t ret;
|
||||
|
||||
state->tune_state = CT_TUNER_START;
|
||||
state->tune_state = CT_TUNER_START;
|
||||
|
||||
do {
|
||||
ret = dib0070_tune_digital(fe, p);
|
||||
if (ret != FE_CALLBACK_TIME_NEVER)
|
||||
msleep(ret/10);
|
||||
else
|
||||
break;
|
||||
} while (state->tune_state != CT_TUNER_STOP);
|
||||
do {
|
||||
ret = dib0070_tune_digital(fe, p);
|
||||
if (ret != FE_CALLBACK_TIME_NEVER)
|
||||
msleep(ret / 10);
|
||||
else
|
||||
break;
|
||||
} while (state->tune_state != CT_TUNER_STOP);
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dib0070_wakeup(struct dvb_frontend *fe)
|
||||
{
|
||||
struct dib0070_state *st = fe->tuner_priv;
|
||||
if (st->cfg->sleep)
|
||||
st->cfg->sleep(fe, 0);
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
if (state->cfg->sleep)
|
||||
state->cfg->sleep(fe, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dib0070_sleep(struct dvb_frontend *fe)
|
||||
{
|
||||
struct dib0070_state *st = fe->tuner_priv;
|
||||
if (st->cfg->sleep)
|
||||
st->cfg->sleep(fe, 1);
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
if (state->cfg->sleep)
|
||||
state->cfg->sleep(fe, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const u16 dib0070_p1f_defaults[] =
|
||||
|
||||
{
|
||||
static const u16 dib0070_p1f_defaults[] = {
|
||||
7, 0x02,
|
||||
0x0008,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0002,
|
||||
0x0100,
|
||||
0x0008,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0002,
|
||||
0x0100,
|
||||
|
||||
3, 0x0d,
|
||||
0x0d80,
|
||||
0x0001,
|
||||
0x0000,
|
||||
0x0d80,
|
||||
0x0001,
|
||||
0x0000,
|
||||
|
||||
4, 0x11,
|
||||
0x0000,
|
||||
0x0103,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0000,
|
||||
0x0103,
|
||||
0x0000,
|
||||
0x0000,
|
||||
|
||||
3, 0x16,
|
||||
0x0004 | 0x0040,
|
||||
0x0030,
|
||||
0x07ff,
|
||||
0x0004 | 0x0040,
|
||||
0x0030,
|
||||
0x07ff,
|
||||
|
||||
6, 0x1b,
|
||||
0x4112,
|
||||
0xff00,
|
||||
0xc07f,
|
||||
0x0000,
|
||||
0x0180,
|
||||
0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
|
||||
0x4112,
|
||||
0xff00,
|
||||
0xc07f,
|
||||
0x0000,
|
||||
0x0180,
|
||||
0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
|
||||
|
||||
0,
|
||||
};
|
||||
|
||||
static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
|
||||
{
|
||||
u16 tuner_en = dib0070_read_reg(state, 0x20);
|
||||
u16 offset;
|
||||
u16 tuner_en = dib0070_read_reg(state, 0x20);
|
||||
u16 offset;
|
||||
|
||||
dib0070_write_reg(state, 0x18, 0x07ff);
|
||||
dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
|
||||
dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
|
||||
msleep(9);
|
||||
offset = dib0070_read_reg(state, 0x19);
|
||||
dib0070_write_reg(state, 0x20, tuner_en);
|
||||
return offset;
|
||||
dib0070_write_reg(state, 0x18, 0x07ff);
|
||||
dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
|
||||
dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
|
||||
msleep(9);
|
||||
offset = dib0070_read_reg(state, 0x19);
|
||||
dib0070_write_reg(state, 0x20, tuner_en);
|
||||
return offset;
|
||||
}
|
||||
|
||||
static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
|
||||
{
|
||||
u8 gain;
|
||||
for (gain = 6; gain < 8; gain++) {
|
||||
state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
|
||||
dprintk( "Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]);
|
||||
}
|
||||
u8 gain;
|
||||
for (gain = 6; gain < 8; gain++) {
|
||||
state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
|
||||
dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain - 6]);
|
||||
}
|
||||
}
|
||||
|
||||
u16 dib0070_wbd_offset(struct dvb_frontend *fe)
|
||||
{
|
||||
struct dib0070_state *st = fe->tuner_priv;
|
||||
return st->wbd_offset_3_3[st->wbd_gain_current - 6];
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
|
||||
u32 freq = fe->dtv_property_cache.frequency / 1000;
|
||||
|
||||
if (tmp != NULL) {
|
||||
while (freq / 1000 > tmp->freq) /* find the right one */
|
||||
tmp++;
|
||||
state->wbd_gain_current = tmp->wbd_gain_val;
|
||||
} else
|
||||
state->wbd_gain_current = 6;
|
||||
|
||||
return state->wbd_offset_3_3[state->wbd_gain_current - 6];
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dib0070_wbd_offset);
|
||||
|
||||
#define pgm_read_word(w) (*w)
|
||||
static int dib0070_reset(struct dvb_frontend *fe)
|
||||
{
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
struct dib0070_state *state = fe->tuner_priv;
|
||||
u16 l, r, *n;
|
||||
|
||||
HARD_RESET(state);
|
||||
|
||||
|
||||
#ifndef FORCE_SBAND_TUNER
|
||||
if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
|
||||
state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
|
||||
|
|
@ -590,13 +605,13 @@ static int dib0070_reset(struct dvb_frontend *fe)
|
|||
#else
|
||||
#warning forcing SBAND
|
||||
#endif
|
||||
state->revision = DIB0070S_P1A;
|
||||
state->revision = DIB0070S_P1A;
|
||||
|
||||
/* P1F or not */
|
||||
dprintk( "Revision: %x", state->revision);
|
||||
dprintk("Revision: %x", state->revision);
|
||||
|
||||
if (state->revision == DIB0070_P1D) {
|
||||
dprintk( "Error: this driver is not to be used meant for P1D or earlier");
|
||||
dprintk("Error: this driver is not to be used meant for P1D or earlier");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -605,7 +620,7 @@ static int dib0070_reset(struct dvb_frontend *fe)
|
|||
while (l) {
|
||||
r = pgm_read_word(n++);
|
||||
do {
|
||||
dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
|
||||
dib0070_write_reg(state, (u8) r, pgm_read_word(n++));
|
||||
r++;
|
||||
} while (--l);
|
||||
l = pgm_read_word(n++);
|
||||
|
|
@ -618,7 +633,6 @@ static int dib0070_reset(struct dvb_frontend *fe)
|
|||
else
|
||||
r = 2;
|
||||
|
||||
|
||||
r |= state->cfg->osc_buffer_state << 3;
|
||||
|
||||
dib0070_write_reg(state, 0x10, r);
|
||||
|
|
@ -629,19 +643,18 @@ static int dib0070_reset(struct dvb_frontend *fe)
|
|||
dib0070_write_reg(state, 0x02, r | (1 << 5));
|
||||
}
|
||||
|
||||
if (state->revision == DIB0070S_P1A)
|
||||
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
|
||||
else
|
||||
if (state->revision == DIB0070S_P1A)
|
||||
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
|
||||
else
|
||||
dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter);
|
||||
|
||||
dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
|
||||
|
||||
dib0070_wbd_offset_calibration(state);
|
||||
dib0070_wbd_offset_calibration(state);
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int dib0070_release(struct dvb_frontend *fe)
|
||||
{
|
||||
kfree(fe->tuner_priv);
|
||||
|
|
@ -651,22 +664,22 @@ static int dib0070_release(struct dvb_frontend *fe)
|
|||
|
||||
static const struct dvb_tuner_ops dib0070_ops = {
|
||||
.info = {
|
||||
.name = "DiBcom DiB0070",
|
||||
.frequency_min = 45000000,
|
||||
.frequency_max = 860000000,
|
||||
.frequency_step = 1000,
|
||||
},
|
||||
.release = dib0070_release,
|
||||
.name = "DiBcom DiB0070",
|
||||
.frequency_min = 45000000,
|
||||
.frequency_max = 860000000,
|
||||
.frequency_step = 1000,
|
||||
},
|
||||
.release = dib0070_release,
|
||||
|
||||
.init = dib0070_wakeup,
|
||||
.sleep = dib0070_sleep,
|
||||
.set_params = dib0070_tune,
|
||||
.init = dib0070_wakeup,
|
||||
.sleep = dib0070_sleep,
|
||||
.set_params = dib0070_tune,
|
||||
|
||||
// .get_frequency = dib0070_get_frequency,
|
||||
// .get_bandwidth = dib0070_get_bandwidth
|
||||
// .get_frequency = dib0070_get_frequency,
|
||||
// .get_bandwidth = dib0070_get_bandwidth
|
||||
};
|
||||
|
||||
struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
|
||||
struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
|
||||
{
|
||||
struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
|
||||
if (state == NULL)
|
||||
|
|
@ -674,7 +687,7 @@ struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
|
|||
|
||||
state->cfg = cfg;
|
||||
state->i2c = i2c;
|
||||
state->fe = fe;
|
||||
state->fe = fe;
|
||||
fe->tuner_priv = state;
|
||||
|
||||
if (dib0070_reset(fe) != 0)
|
||||
|
|
@ -686,11 +699,12 @@ struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter
|
|||
fe->tuner_priv = state;
|
||||
return fe;
|
||||
|
||||
free_mem:
|
||||
free_mem:
|
||||
kfree(state);
|
||||
fe->tuner_priv = NULL;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(dib0070_attach);
|
||||
|
||||
MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ struct i2c_adapter;
|
|||
#define DEFAULT_DIB0070_I2C_ADDRESS 0x60
|
||||
|
||||
struct dib0070_wbd_gain_cfg {
|
||||
u16 freq;
|
||||
u16 wbd_gain_val;
|
||||
u16 freq;
|
||||
u16 wbd_gain_val;
|
||||
};
|
||||
|
||||
struct dib0070_config {
|
||||
|
|
@ -31,32 +31,28 @@ struct dib0070_config {
|
|||
int freq_offset_khz_uhf;
|
||||
int freq_offset_khz_vhf;
|
||||
|
||||
u8 osc_buffer_state; /* 0= normal, 1= tri-state */
|
||||
u32 clock_khz;
|
||||
u8 clock_pad_drive; /* (Drive + 1) * 2mA */
|
||||
u8 osc_buffer_state; /* 0= normal, 1= tri-state */
|
||||
u32 clock_khz;
|
||||
u8 clock_pad_drive; /* (Drive + 1) * 2mA */
|
||||
|
||||
u8 invert_iq; /* invert Q - in case I or Q is inverted on the board */
|
||||
u8 invert_iq; /* invert Q - in case I or Q is inverted on the board */
|
||||
|
||||
u8 force_crystal_mode; /* if == 0 -> decision is made in the driver default: <24 -> 2, >=24 -> 1 */
|
||||
u8 force_crystal_mode; /* if == 0 -> decision is made in the driver default: <24 -> 2, >=24 -> 1 */
|
||||
|
||||
u8 flip_chip;
|
||||
u8 enable_third_order_filter;
|
||||
u8 charge_pump;
|
||||
u8 enable_third_order_filter;
|
||||
u8 charge_pump;
|
||||
|
||||
const struct dib0070_wbd_gain_cfg * wbd_gain;
|
||||
const struct dib0070_wbd_gain_cfg *wbd_gain;
|
||||
|
||||
u8 vga_filter;
|
||||
u8 vga_filter;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DVB_TUNER_DIB0070) || (defined(CONFIG_DVB_TUNER_DIB0070_MODULE) && defined(MODULE))
|
||||
extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe,
|
||||
struct i2c_adapter *i2c,
|
||||
struct dib0070_config *cfg);
|
||||
extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg);
|
||||
extern u16 dib0070_wbd_offset(struct dvb_frontend *);
|
||||
#else
|
||||
static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe,
|
||||
struct i2c_adapter *i2c,
|
||||
struct dib0070_config *cfg)
|
||||
static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
|
||||
{
|
||||
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
|
||||
return NULL;
|
||||
|
|
@ -68,5 +64,6 @@ static inline u16 dib0070_wbd_offset(struct dvb_frontend *fe)
|
|||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
extern void dib0070_ctrl_agc_filter(struct dvb_frontend *, u8 open);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue