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V4L/DVB (9442): Revert back previous change to 90MHz
Note: * At High Symbol Rates we do not have enouph machine cycles to handle the incoming symbols and hence might run into problems at the very end of the specified definition * Most of the equations have been calculated for a master clock of 99 MHz, running at 90MHz, raises lot of issues such as the need to recalculate all of them , which is eventually very painful. Signed-off-by: Manu Abraham <manu@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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3 changed files with 3 additions and 3 deletions
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@ -1575,7 +1575,7 @@ static enum dvbfe_search stb0899_search(struct dvb_frontend *fe, struct dvbfe_pa
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if (i_params->srate <= 5000000)
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stb0899_set_mclk(state, 76500000);
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else
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stb0899_set_mclk(state, 90000000);
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stb0899_set_mclk(state, 99000000);
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switch (state->delsys) {
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case DVBFE_DELSYS_DVBS:
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@ -964,7 +964,7 @@ static const struct stb0899_s1_reg knc1_stb0899_s1_init_1[] = {
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{ STB0899_GPIO37CFG , 0x82 },
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{ STB0899_GPIO38CFG , 0x82 },
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{ STB0899_GPIO39CFG , 0x82 },
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{ STB0899_NCOARSE , 0x13 }, /* 0x13 = 27 Mhz Clock, F/3 = 180MHz, F/6 = 90MHz */
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{ STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
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{ STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
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{ STB0899_FILTCTRL , 0x00 },
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{ STB0899_SYSCTRL , 0x00 },
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@ -1153,7 +1153,7 @@ static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
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{ STB0899_GPIO37CFG , 0x82 },
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{ STB0899_GPIO38CFG , 0x82 },
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{ STB0899_GPIO39CFG , 0x82 },
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{ STB0899_NCOARSE , 0x13 }, /* 0x13 = 27 Mhz Clock, F/3 = 180MHz, F/6 = 90MHz */
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{ STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
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{ STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
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{ STB0899_FILTCTRL , 0x00 },
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{ STB0899_SYSCTRL , 0x00 },
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