mirror of
https://github.com/adulau/aha.git
synced 2024-12-28 11:46:19 +00:00
[PATCH] savagefb: Allocate space for current and saved register states
Allocate space for 2 register states: 'current' for the current state of the hardware, and 'saved', to be used for restoring the hardware to a sane state. This is in preparation for the addition of state save and restore hooks to make savagefb work together with the latest Xorg savage driver. Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Antonino A. Daplas
Linus Torvalds
parent
1ba70a0195
commit
2356614b08
2 changed files with 328 additions and 324 deletions
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@ -147,77 +147,7 @@ struct xtimings {
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int interlaced;
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};
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/* --------------------------------------------------------------------- */
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#define NR_PALETTE 256
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struct savagefb_par;
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struct savagefb_i2c_chan {
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struct savagefb_par *par;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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volatile u8 __iomem *ioaddr;
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u32 reg;
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};
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struct savagefb_par {
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struct pci_dev *pcidev;
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savage_chipset chip;
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struct savagefb_i2c_chan chan;
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unsigned char *edid;
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u32 pseudo_palette[16];
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int paletteEnabled;
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int pm_state;
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int display_type;
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int dvi;
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int crtonly;
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int dacSpeedBpp;
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int maxClock;
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int minClock;
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int numClocks;
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int clock[4];
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struct {
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u8 __iomem *vbase;
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u32 pbase;
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u32 len;
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#ifdef CONFIG_MTRR
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int mtrr;
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#endif
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} video;
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struct {
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volatile u8 __iomem *vbase;
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u32 pbase;
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u32 len;
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} mmio;
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volatile u32 __iomem *bci_base;
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unsigned int bci_ptr;
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u32 cob_offset;
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u32 cob_size;
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int cob_index;
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void (*SavageWaitIdle) (struct savagefb_par *par);
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void (*SavageWaitFifo) (struct savagefb_par *par, int space);
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int MCLK, REFCLK, LCDclk;
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int HorizScaleFactor;
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/* Panels size */
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int SavagePanelWidth;
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int SavagePanelHeight;
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struct {
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u16 red, green, blue, transp;
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} palette[NR_PALETTE];
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int depth;
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int vwidth;
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struct savage_reg {
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unsigned char MiscOutReg; /* Misc */
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unsigned char CRTC[25]; /* Crtc Controller */
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unsigned char Sequencer[5]; /* Video Sequencer */
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@ -238,6 +168,77 @@ struct savagefb_par {
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unsigned int STREAMS[22]; /* yuck, streams regs */
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unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
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};
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/* --------------------------------------------------------------------- */
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#define NR_PALETTE 256
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struct savagefb_par;
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struct savagefb_i2c_chan {
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struct savagefb_par *par;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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volatile u8 __iomem *ioaddr;
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u32 reg;
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};
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struct savagefb_par {
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struct pci_dev *pcidev;
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savage_chipset chip;
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struct savagefb_i2c_chan chan;
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struct savage_reg state;
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struct savage_reg save;
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unsigned char *edid;
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u32 pseudo_palette[16];
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int paletteEnabled;
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int pm_state;
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int display_type;
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int dvi;
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int crtonly;
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int dacSpeedBpp;
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int maxClock;
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int minClock;
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int numClocks;
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int clock[4];
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int MCLK, REFCLK, LCDclk;
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struct {
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u8 __iomem *vbase;
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u32 pbase;
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u32 len;
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#ifdef CONFIG_MTRR
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int mtrr;
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#endif
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} video;
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struct {
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volatile u8 __iomem *vbase;
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u32 pbase;
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u32 len;
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} mmio;
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volatile u32 __iomem *bci_base;
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unsigned int bci_ptr;
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u32 cob_offset;
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u32 cob_size;
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int cob_index;
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void (*SavageWaitIdle) (struct savagefb_par *par);
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void (*SavageWaitFifo) (struct savagefb_par *par, int space);
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int HorizScaleFactor;
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/* Panels size */
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int SavagePanelWidth;
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int SavagePanelHeight;
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struct {
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u16 red, green, blue, transp;
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} palette[NR_PALETTE];
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int depth;
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int vwidth;
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};
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#define BCI_BD_BW_DISABLE 0x10000000
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#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
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@ -122,66 +122,67 @@ static void vgaHWProtect (struct savagefb_par *par, int on)
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}
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}
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static void vgaHWRestore (struct savagefb_par *par)
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static void vgaHWRestore (struct savagefb_par *par, struct savage_reg *reg)
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{
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int i;
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VGAwMISC (par->MiscOutReg, par);
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VGAwMISC (reg->MiscOutReg, par);
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for (i = 1; i < 5; i++)
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VGAwSEQ (i, par->Sequencer[i], par);
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VGAwSEQ (i, reg->Sequencer[i], par);
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/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
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CRTC[17] */
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VGAwCR (17, par->CRTC[17] & ~0x80, par);
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VGAwCR (17, reg->CRTC[17] & ~0x80, par);
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for (i = 0; i < 25; i++)
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VGAwCR (i, par->CRTC[i], par);
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VGAwCR (i, reg->CRTC[i], par);
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for (i = 0; i < 9; i++)
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VGAwGR (i, par->Graphics[i], par);
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VGAwGR (i, reg->Graphics[i], par);
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VGAenablePalette(par);
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for (i = 0; i < 21; i++)
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VGAwATTR (i, par->Attribute[i], par);
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VGAwATTR (i, reg->Attribute[i], par);
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VGAdisablePalette(par);
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}
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static void vgaHWInit (struct fb_var_screeninfo *var,
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struct savagefb_par *par,
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struct xtimings *timings)
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struct xtimings *timings,
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struct savage_reg *reg)
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{
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par->MiscOutReg = 0x23;
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reg->MiscOutReg = 0x23;
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if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
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par->MiscOutReg |= 0x40;
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reg->MiscOutReg |= 0x40;
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if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
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par->MiscOutReg |= 0x80;
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reg->MiscOutReg |= 0x80;
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/*
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* Time Sequencer
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*/
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par->Sequencer[0x00] = 0x00;
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par->Sequencer[0x01] = 0x01;
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par->Sequencer[0x02] = 0x0F;
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par->Sequencer[0x03] = 0x00; /* Font select */
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par->Sequencer[0x04] = 0x0E; /* Misc */
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reg->Sequencer[0x00] = 0x00;
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reg->Sequencer[0x01] = 0x01;
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reg->Sequencer[0x02] = 0x0F;
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reg->Sequencer[0x03] = 0x00; /* Font select */
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reg->Sequencer[0x04] = 0x0E; /* Misc */
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/*
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* CRTC Controller
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*/
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par->CRTC[0x00] = (timings->HTotal >> 3) - 5;
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par->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
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par->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
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par->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
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par->CRTC[0x04] = (timings->HSyncStart >> 3);
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par->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
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reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
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reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
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reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
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reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
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reg->CRTC[0x04] = (timings->HSyncStart >> 3);
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reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
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(((timings->HSyncEnd >> 3)) & 0x1f);
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par->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
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par->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
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reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
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reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
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(((timings->VDisplay - 1) & 0x100) >> 7) |
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((timings->VSyncStart & 0x100) >> 6) |
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(((timings->VSyncStart - 1) & 0x100) >> 5) |
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@ -189,27 +190,27 @@ static void vgaHWInit (struct fb_var_screeninfo *var,
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(((timings->VTotal - 2) & 0x200) >> 4) |
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(((timings->VDisplay - 1) & 0x200) >> 3) |
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((timings->VSyncStart & 0x200) >> 2);
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par->CRTC[0x08] = 0x00;
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par->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
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reg->CRTC[0x08] = 0x00;
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reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
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if (timings->dblscan)
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par->CRTC[0x09] |= 0x80;
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reg->CRTC[0x09] |= 0x80;
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par->CRTC[0x0a] = 0x00;
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par->CRTC[0x0b] = 0x00;
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par->CRTC[0x0c] = 0x00;
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par->CRTC[0x0d] = 0x00;
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par->CRTC[0x0e] = 0x00;
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par->CRTC[0x0f] = 0x00;
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par->CRTC[0x10] = timings->VSyncStart & 0xff;
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par->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
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par->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
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par->CRTC[0x13] = var->xres_virtual >> 4;
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par->CRTC[0x14] = 0x00;
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par->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
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par->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
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par->CRTC[0x17] = 0xc3;
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par->CRTC[0x18] = 0xff;
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reg->CRTC[0x0a] = 0x00;
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reg->CRTC[0x0b] = 0x00;
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reg->CRTC[0x0c] = 0x00;
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reg->CRTC[0x0d] = 0x00;
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reg->CRTC[0x0e] = 0x00;
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reg->CRTC[0x0f] = 0x00;
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reg->CRTC[0x10] = timings->VSyncStart & 0xff;
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reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
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reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
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reg->CRTC[0x13] = var->xres_virtual >> 4;
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reg->CRTC[0x14] = 0x00;
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reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
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reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
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reg->CRTC[0x17] = 0xc3;
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reg->CRTC[0x18] = 0xff;
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/*
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* are these unnecessary?
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@ -220,38 +221,38 @@ static void vgaHWInit (struct fb_var_screeninfo *var,
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/*
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* Graphics Display Controller
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*/
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par->Graphics[0x00] = 0x00;
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par->Graphics[0x01] = 0x00;
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par->Graphics[0x02] = 0x00;
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par->Graphics[0x03] = 0x00;
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par->Graphics[0x04] = 0x00;
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par->Graphics[0x05] = 0x40;
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par->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
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par->Graphics[0x07] = 0x0F;
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par->Graphics[0x08] = 0xFF;
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reg->Graphics[0x00] = 0x00;
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reg->Graphics[0x01] = 0x00;
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reg->Graphics[0x02] = 0x00;
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reg->Graphics[0x03] = 0x00;
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reg->Graphics[0x04] = 0x00;
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reg->Graphics[0x05] = 0x40;
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reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
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reg->Graphics[0x07] = 0x0F;
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reg->Graphics[0x08] = 0xFF;
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par->Attribute[0x00] = 0x00; /* standard colormap translation */
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par->Attribute[0x01] = 0x01;
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par->Attribute[0x02] = 0x02;
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par->Attribute[0x03] = 0x03;
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par->Attribute[0x04] = 0x04;
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par->Attribute[0x05] = 0x05;
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par->Attribute[0x06] = 0x06;
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par->Attribute[0x07] = 0x07;
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par->Attribute[0x08] = 0x08;
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par->Attribute[0x09] = 0x09;
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par->Attribute[0x0a] = 0x0A;
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par->Attribute[0x0b] = 0x0B;
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par->Attribute[0x0c] = 0x0C;
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par->Attribute[0x0d] = 0x0D;
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par->Attribute[0x0e] = 0x0E;
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par->Attribute[0x0f] = 0x0F;
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par->Attribute[0x10] = 0x41;
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par->Attribute[0x11] = 0xFF;
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par->Attribute[0x12] = 0x0F;
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par->Attribute[0x13] = 0x00;
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par->Attribute[0x14] = 0x00;
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reg->Attribute[0x00] = 0x00; /* standard colormap translation */
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reg->Attribute[0x01] = 0x01;
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reg->Attribute[0x02] = 0x02;
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reg->Attribute[0x03] = 0x03;
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reg->Attribute[0x04] = 0x04;
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reg->Attribute[0x05] = 0x05;
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reg->Attribute[0x06] = 0x06;
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reg->Attribute[0x07] = 0x07;
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reg->Attribute[0x08] = 0x08;
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reg->Attribute[0x09] = 0x09;
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reg->Attribute[0x0a] = 0x0A;
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reg->Attribute[0x0b] = 0x0B;
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reg->Attribute[0x0c] = 0x0C;
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reg->Attribute[0x0d] = 0x0D;
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reg->Attribute[0x0e] = 0x0E;
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reg->Attribute[0x0f] = 0x0F;
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reg->Attribute[0x10] = 0x41;
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reg->Attribute[0x11] = 0xFF;
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reg->Attribute[0x12] = 0x0F;
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reg->Attribute[0x13] = 0x00;
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reg->Attribute[0x14] = 0x00;
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}
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/* -------------------- Hardware specific routines ------------------------- */
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@ -513,7 +514,7 @@ static void SavagePrintRegs(void)
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/* --------------------------------------------------------------------- */
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static void savage_get_default_par(struct savagefb_par *par)
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static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
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{
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unsigned char cr3a, cr53, cr66;
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@ -543,96 +544,96 @@ static void savage_get_default_par(struct savagefb_par *par)
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/* unlock extended seq regs */
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vga_out8 (0x3c4, 0x08, par);
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par->SR08 = vga_in8 (0x3c5, par);
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reg->SR08 = vga_in8 (0x3c5, par);
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vga_out8 (0x3c5, 0x06, par);
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/* now save all the extended regs we need */
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vga_out8 (0x3d4, 0x31, par);
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par->CR31 = vga_in8 (0x3d5, par);
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reg->CR31 = vga_in8 (0x3d5, par);
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vga_out8 (0x3d4, 0x32, par);
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par->CR32 = vga_in8 (0x3d5, par);
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reg->CR32 = vga_in8 (0x3d5, par);
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vga_out8 (0x3d4, 0x34, par);
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par->CR34 = vga_in8 (0x3d5, par);
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reg->CR34 = vga_in8 (0x3d5, par);
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vga_out8 (0x3d4, 0x36, par);
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par->CR36 = vga_in8 (0x3d5, par);
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reg->CR36 = vga_in8 (0x3d5, par);
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vga_out8 (0x3d4, 0x3a, par);
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par->CR3A = vga_in8 (0x3d5, par);
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reg->CR3A = vga_in8 (0x3d5, par);
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vga_out8 (0x3d4, 0x40, par);
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par->CR40 = vga_in8 (0x3d5, par);
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reg->CR40 = vga_in8 (0x3d5, par);
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vga_out8 (0x3d4, 0x42, par);
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par->CR42 = vga_in8 (0x3d5, par);
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reg->CR42 = vga_in8 (0x3d5, par);
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vga_out8 (0x3d4, 0x45, par);
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par->CR45 = vga_in8 (0x3d5, par);
|
||||
reg->CR45 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x50, par);
|
||||
par->CR50 = vga_in8 (0x3d5, par);
|
||||
reg->CR50 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x51, par);
|
||||
par->CR51 = vga_in8 (0x3d5, par);
|
||||
reg->CR51 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x53, par);
|
||||
par->CR53 = vga_in8 (0x3d5, par);
|
||||
reg->CR53 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x58, par);
|
||||
par->CR58 = vga_in8 (0x3d5, par);
|
||||
reg->CR58 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x60, par);
|
||||
par->CR60 = vga_in8 (0x3d5, par);
|
||||
reg->CR60 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x66, par);
|
||||
par->CR66 = vga_in8 (0x3d5, par);
|
||||
reg->CR66 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x67, par);
|
||||
par->CR67 = vga_in8 (0x3d5, par);
|
||||
reg->CR67 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x68, par);
|
||||
par->CR68 = vga_in8 (0x3d5, par);
|
||||
reg->CR68 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x69, par);
|
||||
par->CR69 = vga_in8 (0x3d5, par);
|
||||
reg->CR69 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x6f, par);
|
||||
par->CR6F = vga_in8 (0x3d5, par);
|
||||
reg->CR6F = vga_in8 (0x3d5, par);
|
||||
|
||||
vga_out8 (0x3d4, 0x33, par);
|
||||
par->CR33 = vga_in8 (0x3d5, par);
|
||||
reg->CR33 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x86, par);
|
||||
par->CR86 = vga_in8 (0x3d5, par);
|
||||
reg->CR86 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x88, par);
|
||||
par->CR88 = vga_in8 (0x3d5, par);
|
||||
reg->CR88 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x90, par);
|
||||
par->CR90 = vga_in8 (0x3d5, par);
|
||||
reg->CR90 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x91, par);
|
||||
par->CR91 = vga_in8 (0x3d5, par);
|
||||
reg->CR91 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0xb0, par);
|
||||
par->CRB0 = vga_in8 (0x3d5, par) | 0x80;
|
||||
reg->CRB0 = vga_in8 (0x3d5, par) | 0x80;
|
||||
|
||||
/* extended mode timing regs */
|
||||
vga_out8 (0x3d4, 0x3b, par);
|
||||
par->CR3B = vga_in8 (0x3d5, par);
|
||||
reg->CR3B = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x3c, par);
|
||||
par->CR3C = vga_in8 (0x3d5, par);
|
||||
reg->CR3C = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x43, par);
|
||||
par->CR43 = vga_in8 (0x3d5, par);
|
||||
reg->CR43 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x5d, par);
|
||||
par->CR5D = vga_in8 (0x3d5, par);
|
||||
reg->CR5D = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x5e, par);
|
||||
par->CR5E = vga_in8 (0x3d5, par);
|
||||
reg->CR5E = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x65, par);
|
||||
par->CR65 = vga_in8 (0x3d5, par);
|
||||
reg->CR65 = vga_in8 (0x3d5, par);
|
||||
|
||||
/* save seq extended regs for DCLK PLL programming */
|
||||
vga_out8 (0x3c4, 0x0e, par);
|
||||
par->SR0E = vga_in8 (0x3c5, par);
|
||||
reg->SR0E = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x0f, par);
|
||||
par->SR0F = vga_in8 (0x3c5, par);
|
||||
reg->SR0F = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x10, par);
|
||||
par->SR10 = vga_in8 (0x3c5, par);
|
||||
reg->SR10 = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x11, par);
|
||||
par->SR11 = vga_in8 (0x3c5, par);
|
||||
reg->SR11 = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x12, par);
|
||||
par->SR12 = vga_in8 (0x3c5, par);
|
||||
reg->SR12 = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x13, par);
|
||||
par->SR13 = vga_in8 (0x3c5, par);
|
||||
reg->SR13 = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x29, par);
|
||||
par->SR29 = vga_in8 (0x3c5, par);
|
||||
reg->SR29 = vga_in8 (0x3c5, par);
|
||||
|
||||
vga_out8 (0x3c4, 0x15, par);
|
||||
par->SR15 = vga_in8 (0x3c5, par);
|
||||
reg->SR15 = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x30, par);
|
||||
par->SR30 = vga_in8 (0x3c5, par);
|
||||
reg->SR30 = vga_in8 (0x3c5, par);
|
||||
vga_out8 (0x3c4, 0x18, par);
|
||||
par->SR18 = vga_in8 (0x3c5, par);
|
||||
reg->SR18 = vga_in8 (0x3c5, par);
|
||||
|
||||
/* Save flat panel expansion regsters. */
|
||||
if (par->chip == S3_SAVAGE_MX) {
|
||||
|
|
@ -640,7 +641,7 @@ static void savage_get_default_par(struct savagefb_par *par)
|
|||
|
||||
for (i = 0; i < 8; i++) {
|
||||
vga_out8 (0x3c4, 0x54+i, par);
|
||||
par->SR54[i] = vga_in8 (0x3c5, par);
|
||||
reg->SR54[i] = vga_in8 (0x3c5, par);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -653,10 +654,10 @@ static void savage_get_default_par(struct savagefb_par *par)
|
|||
|
||||
/* now save MIU regs */
|
||||
if (par->chip != S3_SAVAGE_MX) {
|
||||
par->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
|
||||
par->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
|
||||
par->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
|
||||
par->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
|
||||
reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
|
||||
reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
|
||||
reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
|
||||
reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
|
||||
}
|
||||
|
||||
vga_out8 (0x3d4, 0x3a, par);
|
||||
|
|
@ -789,7 +790,8 @@ static int savagefb_check_var (struct fb_var_screeninfo *var,
|
|||
|
||||
|
||||
static int savagefb_decode_var (struct fb_var_screeninfo *var,
|
||||
struct savagefb_par *par)
|
||||
struct savagefb_par *par,
|
||||
struct savage_reg *reg)
|
||||
{
|
||||
struct xtimings timings;
|
||||
int width, dclk, i, j; /*, refresh; */
|
||||
|
|
@ -831,39 +833,39 @@ static int savagefb_decode_var (struct fb_var_screeninfo *var,
|
|||
* This will allocate the datastructure and initialize all of the
|
||||
* generic VGA registers.
|
||||
*/
|
||||
vgaHWInit (var, par, &timings);
|
||||
vgaHWInit (var, par, &timings, reg);
|
||||
|
||||
/* We need to set CR67 whether or not we use the BIOS. */
|
||||
|
||||
dclk = timings.Clock;
|
||||
par->CR67 = 0x00;
|
||||
reg->CR67 = 0x00;
|
||||
|
||||
switch( var->bits_per_pixel ) {
|
||||
case 8:
|
||||
if( (par->chip == S3_SAVAGE2000) && (dclk >= 230000) )
|
||||
par->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
|
||||
reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
|
||||
else
|
||||
par->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
|
||||
reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
|
||||
break;
|
||||
case 15:
|
||||
if ( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
|
||||
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
|
||||
par->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
|
||||
reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
|
||||
else
|
||||
par->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
|
||||
reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
|
||||
break;
|
||||
case 16:
|
||||
if( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
|
||||
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
|
||||
par->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
|
||||
reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
|
||||
else
|
||||
par->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
|
||||
reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
|
||||
break;
|
||||
case 24:
|
||||
par->CR67 = 0x70;
|
||||
reg->CR67 = 0x70;
|
||||
break;
|
||||
case 32:
|
||||
par->CR67 = 0xd0;
|
||||
reg->CR67 = 0xd0;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -875,58 +877,58 @@ static int savagefb_decode_var (struct fb_var_screeninfo *var,
|
|||
vga_out8 (0x3d4, 0x3a, par);
|
||||
tmp = vga_in8 (0x3d5, par);
|
||||
if (1 /*FIXME:psav->pci_burst*/)
|
||||
par->CR3A = (tmp & 0x7f) | 0x15;
|
||||
reg->CR3A = (tmp & 0x7f) | 0x15;
|
||||
else
|
||||
par->CR3A = tmp | 0x95;
|
||||
reg->CR3A = tmp | 0x95;
|
||||
|
||||
par->CR53 = 0x00;
|
||||
par->CR31 = 0x8c;
|
||||
par->CR66 = 0x89;
|
||||
reg->CR53 = 0x00;
|
||||
reg->CR31 = 0x8c;
|
||||
reg->CR66 = 0x89;
|
||||
|
||||
vga_out8 (0x3d4, 0x58, par);
|
||||
par->CR58 = vga_in8 (0x3d5, par) & 0x80;
|
||||
par->CR58 |= 0x13;
|
||||
reg->CR58 = vga_in8 (0x3d5, par) & 0x80;
|
||||
reg->CR58 |= 0x13;
|
||||
|
||||
par->SR15 = 0x03 | 0x80;
|
||||
par->SR18 = 0x00;
|
||||
par->CR43 = par->CR45 = par->CR65 = 0x00;
|
||||
reg->SR15 = 0x03 | 0x80;
|
||||
reg->SR18 = 0x00;
|
||||
reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
|
||||
|
||||
vga_out8 (0x3d4, 0x40, par);
|
||||
par->CR40 = vga_in8 (0x3d5, par) & ~0x01;
|
||||
reg->CR40 = vga_in8 (0x3d5, par) & ~0x01;
|
||||
|
||||
par->MMPR0 = 0x010400;
|
||||
par->MMPR1 = 0x00;
|
||||
par->MMPR2 = 0x0808;
|
||||
par->MMPR3 = 0x08080810;
|
||||
reg->MMPR0 = 0x010400;
|
||||
reg->MMPR1 = 0x00;
|
||||
reg->MMPR2 = 0x0808;
|
||||
reg->MMPR3 = 0x08080810;
|
||||
|
||||
SavageCalcClock (dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
|
||||
/* m = 107; n = 4; r = 2; */
|
||||
|
||||
if (par->MCLK <= 0) {
|
||||
par->SR10 = 255;
|
||||
par->SR11 = 255;
|
||||
reg->SR10 = 255;
|
||||
reg->SR11 = 255;
|
||||
} else {
|
||||
common_calc_clock (par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
|
||||
&par->SR11, &par->SR10);
|
||||
/* par->SR10 = 80; // MCLK == 286000 */
|
||||
/* par->SR11 = 125; */
|
||||
®->SR11, ®->SR10);
|
||||
/* reg->SR10 = 80; // MCLK == 286000 */
|
||||
/* reg->SR11 = 125; */
|
||||
}
|
||||
|
||||
par->SR12 = (r << 6) | (n & 0x3f);
|
||||
par->SR13 = m & 0xff;
|
||||
par->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
|
||||
reg->SR12 = (r << 6) | (n & 0x3f);
|
||||
reg->SR13 = m & 0xff;
|
||||
reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
|
||||
|
||||
if (var->bits_per_pixel < 24)
|
||||
par->MMPR0 -= 0x8000;
|
||||
reg->MMPR0 -= 0x8000;
|
||||
else
|
||||
par->MMPR0 -= 0x4000;
|
||||
reg->MMPR0 -= 0x4000;
|
||||
|
||||
if (timings.interlaced)
|
||||
par->CR42 = 0x20;
|
||||
reg->CR42 = 0x20;
|
||||
else
|
||||
par->CR42 = 0x00;
|
||||
reg->CR42 = 0x00;
|
||||
|
||||
par->CR34 = 0x10; /* display fifo */
|
||||
reg->CR34 = 0x10; /* display fifo */
|
||||
|
||||
i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
|
||||
((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
|
||||
|
|
@ -938,77 +940,77 @@ static int savagefb_decode_var (struct fb_var_screeninfo *var,
|
|||
if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
|
||||
i |= 0x20;
|
||||
|
||||
j = (par->CRTC[0] + ((i & 0x01) << 8) +
|
||||
par->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
|
||||
j = (reg->CRTC[0] + ((i & 0x01) << 8) +
|
||||
reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
|
||||
|
||||
if (j - (par->CRTC[4] + ((i & 0x10) << 4)) < 4) {
|
||||
if (par->CRTC[4] + ((i & 0x10) << 4) + 4 <=
|
||||
par->CRTC[0] + ((i & 0x01) << 8))
|
||||
j = par->CRTC[4] + ((i & 0x10) << 4) + 4;
|
||||
if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
|
||||
if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
|
||||
reg->CRTC[0] + ((i & 0x01) << 8))
|
||||
j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
|
||||
else
|
||||
j = par->CRTC[0] + ((i & 0x01) << 8) + 1;
|
||||
j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
|
||||
}
|
||||
|
||||
par->CR3B = j & 0xff;
|
||||
reg->CR3B = j & 0xff;
|
||||
i |= (j & 0x100) >> 2;
|
||||
par->CR3C = (par->CRTC[0] + ((i & 0x01) << 8)) / 2;
|
||||
par->CR5D = i;
|
||||
par->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
|
||||
reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
|
||||
reg->CR5D = i;
|
||||
reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
|
||||
(((timings.VDisplay - 1) & 0x400) >> 9) |
|
||||
(((timings.VSyncStart) & 0x400) >> 8) |
|
||||
(((timings.VSyncStart) & 0x400) >> 6) | 0x40;
|
||||
width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
|
||||
par->CR91 = par->CRTC[19] = 0xff & width;
|
||||
par->CR51 = (0x300 & width) >> 4;
|
||||
par->CR90 = 0x80 | (width >> 8);
|
||||
par->MiscOutReg |= 0x0c;
|
||||
reg->CR91 = reg->CRTC[19] = 0xff & width;
|
||||
reg->CR51 = (0x300 & width) >> 4;
|
||||
reg->CR90 = 0x80 | (width >> 8);
|
||||
reg->MiscOutReg |= 0x0c;
|
||||
|
||||
/* Set frame buffer description. */
|
||||
|
||||
if (var->bits_per_pixel <= 8)
|
||||
par->CR50 = 0;
|
||||
reg->CR50 = 0;
|
||||
else if (var->bits_per_pixel <= 16)
|
||||
par->CR50 = 0x10;
|
||||
reg->CR50 = 0x10;
|
||||
else
|
||||
par->CR50 = 0x30;
|
||||
reg->CR50 = 0x30;
|
||||
|
||||
if (var->xres_virtual <= 640)
|
||||
par->CR50 |= 0x40;
|
||||
reg->CR50 |= 0x40;
|
||||
else if (var->xres_virtual == 800)
|
||||
par->CR50 |= 0x80;
|
||||
reg->CR50 |= 0x80;
|
||||
else if (var->xres_virtual == 1024)
|
||||
par->CR50 |= 0x00;
|
||||
reg->CR50 |= 0x00;
|
||||
else if (var->xres_virtual == 1152)
|
||||
par->CR50 |= 0x01;
|
||||
reg->CR50 |= 0x01;
|
||||
else if (var->xres_virtual == 1280)
|
||||
par->CR50 |= 0xc0;
|
||||
reg->CR50 |= 0xc0;
|
||||
else if (var->xres_virtual == 1600)
|
||||
par->CR50 |= 0x81;
|
||||
reg->CR50 |= 0x81;
|
||||
else
|
||||
par->CR50 |= 0xc1; /* Use GBD */
|
||||
reg->CR50 |= 0xc1; /* Use GBD */
|
||||
|
||||
if( par->chip == S3_SAVAGE2000 )
|
||||
par->CR33 = 0x08;
|
||||
reg->CR33 = 0x08;
|
||||
else
|
||||
par->CR33 = 0x20;
|
||||
reg->CR33 = 0x20;
|
||||
|
||||
par->CRTC[0x17] = 0xeb;
|
||||
reg->CRTC[0x17] = 0xeb;
|
||||
|
||||
par->CR67 |= 1;
|
||||
reg->CR67 |= 1;
|
||||
|
||||
vga_out8(0x3d4, 0x36, par);
|
||||
par->CR36 = vga_in8 (0x3d5, par);
|
||||
reg->CR36 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x68, par);
|
||||
par->CR68 = vga_in8 (0x3d5, par);
|
||||
par->CR69 = 0;
|
||||
reg->CR68 = vga_in8 (0x3d5, par);
|
||||
reg->CR69 = 0;
|
||||
vga_out8 (0x3d4, 0x6f, par);
|
||||
par->CR6F = vga_in8 (0x3d5, par);
|
||||
reg->CR6F = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x86, par);
|
||||
par->CR86 = vga_in8 (0x3d5, par);
|
||||
reg->CR86 = vga_in8 (0x3d5, par);
|
||||
vga_out8 (0x3d4, 0x88, par);
|
||||
par->CR88 = vga_in8 (0x3d5, par) | 0x08;
|
||||
reg->CR88 = vga_in8 (0x3d5, par) | 0x08;
|
||||
vga_out8 (0x3d4, 0xb0, par);
|
||||
par->CRB0 = vga_in8 (0x3d5, par) | 0x80;
|
||||
reg->CRB0 = vga_in8 (0x3d5, par) | 0x80;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1075,7 +1077,7 @@ static int savagefb_setcolreg(unsigned regno,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void savagefb_set_par_int (struct savagefb_par *par)
|
||||
static void savagefb_set_par_int (struct savagefb_par *par, struct savage_reg *reg)
|
||||
{
|
||||
unsigned char tmp, cr3a, cr66, cr67;
|
||||
|
||||
|
|
@ -1110,30 +1112,30 @@ static void savagefb_set_par_int (struct savagefb_par *par)
|
|||
|
||||
/* restore extended regs */
|
||||
vga_out8 (0x3d4, 0x66, par);
|
||||
vga_out8 (0x3d5, par->CR66, par);
|
||||
vga_out8 (0x3d5, reg->CR66, par);
|
||||
vga_out8 (0x3d4, 0x3a, par);
|
||||
vga_out8 (0x3d5, par->CR3A, par);
|
||||
vga_out8 (0x3d5, reg->CR3A, par);
|
||||
vga_out8 (0x3d4, 0x31, par);
|
||||
vga_out8 (0x3d5, par->CR31, par);
|
||||
vga_out8 (0x3d5, reg->CR31, par);
|
||||
vga_out8 (0x3d4, 0x32, par);
|
||||
vga_out8 (0x3d5, par->CR32, par);
|
||||
vga_out8 (0x3d5, reg->CR32, par);
|
||||
vga_out8 (0x3d4, 0x58, par);
|
||||
vga_out8 (0x3d5, par->CR58, par);
|
||||
vga_out8 (0x3d5, reg->CR58, par);
|
||||
vga_out8 (0x3d4, 0x53, par);
|
||||
vga_out8 (0x3d5, par->CR53 & 0x7f, par);
|
||||
vga_out8 (0x3d5, reg->CR53 & 0x7f, par);
|
||||
|
||||
vga_out16 (0x3c4, 0x0608, par);
|
||||
|
||||
/* Restore DCLK registers. */
|
||||
|
||||
vga_out8 (0x3c4, 0x0e, par);
|
||||
vga_out8 (0x3c5, par->SR0E, par);
|
||||
vga_out8 (0x3c5, reg->SR0E, par);
|
||||
vga_out8 (0x3c4, 0x0f, par);
|
||||
vga_out8 (0x3c5, par->SR0F, par);
|
||||
vga_out8 (0x3c5, reg->SR0F, par);
|
||||
vga_out8 (0x3c4, 0x29, par);
|
||||
vga_out8 (0x3c5, par->SR29, par);
|
||||
vga_out8 (0x3c5, reg->SR29, par);
|
||||
vga_out8 (0x3c4, 0x15, par);
|
||||
vga_out8 (0x3c5, par->SR15, par);
|
||||
vga_out8 (0x3c5, reg->SR15, par);
|
||||
|
||||
/* Restore flat panel expansion regsters. */
|
||||
if( par->chip == S3_SAVAGE_MX ) {
|
||||
|
|
@ -1141,27 +1143,27 @@ static void savagefb_set_par_int (struct savagefb_par *par)
|
|||
|
||||
for( i = 0; i < 8; i++ ) {
|
||||
vga_out8 (0x3c4, 0x54+i, par);
|
||||
vga_out8 (0x3c5, par->SR54[i], par);
|
||||
vga_out8 (0x3c5, reg->SR54[i], par);
|
||||
}
|
||||
}
|
||||
|
||||
vgaHWRestore (par);
|
||||
vgaHWRestore (par, reg);
|
||||
|
||||
/* extended mode timing registers */
|
||||
vga_out8 (0x3d4, 0x53, par);
|
||||
vga_out8 (0x3d5, par->CR53, par);
|
||||
vga_out8 (0x3d5, reg->CR53, par);
|
||||
vga_out8 (0x3d4, 0x5d, par);
|
||||
vga_out8 (0x3d5, par->CR5D, par);
|
||||
vga_out8 (0x3d5, reg->CR5D, par);
|
||||
vga_out8 (0x3d4, 0x5e, par);
|
||||
vga_out8 (0x3d5, par->CR5E, par);
|
||||
vga_out8 (0x3d5, reg->CR5E, par);
|
||||
vga_out8 (0x3d4, 0x3b, par);
|
||||
vga_out8 (0x3d5, par->CR3B, par);
|
||||
vga_out8 (0x3d5, reg->CR3B, par);
|
||||
vga_out8 (0x3d4, 0x3c, par);
|
||||
vga_out8 (0x3d5, par->CR3C, par);
|
||||
vga_out8 (0x3d5, reg->CR3C, par);
|
||||
vga_out8 (0x3d4, 0x43, par);
|
||||
vga_out8 (0x3d5, par->CR43, par);
|
||||
vga_out8 (0x3d5, reg->CR43, par);
|
||||
vga_out8 (0x3d4, 0x65, par);
|
||||
vga_out8 (0x3d5, par->CR65, par);
|
||||
vga_out8 (0x3d5, reg->CR65, par);
|
||||
|
||||
/* restore the desired video mode with cr67 */
|
||||
vga_out8 (0x3d4, 0x67, par);
|
||||
|
|
@ -1171,52 +1173,52 @@ static void savagefb_set_par_int (struct savagefb_par *par)
|
|||
udelay (10000);
|
||||
vga_out8 (0x3d4, 0x67, par);
|
||||
/* end of part */
|
||||
vga_out8 (0x3d5, par->CR67 & ~0x0c, par);
|
||||
vga_out8 (0x3d5, reg->CR67 & ~0x0c, par);
|
||||
|
||||
/* other mode timing and extended regs */
|
||||
vga_out8 (0x3d4, 0x34, par);
|
||||
vga_out8 (0x3d5, par->CR34, par);
|
||||
vga_out8 (0x3d5, reg->CR34, par);
|
||||
vga_out8 (0x3d4, 0x40, par);
|
||||
vga_out8 (0x3d5, par->CR40, par);
|
||||
vga_out8 (0x3d5, reg->CR40, par);
|
||||
vga_out8 (0x3d4, 0x42, par);
|
||||
vga_out8 (0x3d5, par->CR42, par);
|
||||
vga_out8 (0x3d5, reg->CR42, par);
|
||||
vga_out8 (0x3d4, 0x45, par);
|
||||
vga_out8 (0x3d5, par->CR45, par);
|
||||
vga_out8 (0x3d5, reg->CR45, par);
|
||||
vga_out8 (0x3d4, 0x50, par);
|
||||
vga_out8 (0x3d5, par->CR50, par);
|
||||
vga_out8 (0x3d5, reg->CR50, par);
|
||||
vga_out8 (0x3d4, 0x51, par);
|
||||
vga_out8 (0x3d5, par->CR51, par);
|
||||
vga_out8 (0x3d5, reg->CR51, par);
|
||||
|
||||
/* memory timings */
|
||||
vga_out8 (0x3d4, 0x36, par);
|
||||
vga_out8 (0x3d5, par->CR36, par);
|
||||
vga_out8 (0x3d5, reg->CR36, par);
|
||||
vga_out8 (0x3d4, 0x60, par);
|
||||
vga_out8 (0x3d5, par->CR60, par);
|
||||
vga_out8 (0x3d5, reg->CR60, par);
|
||||
vga_out8 (0x3d4, 0x68, par);
|
||||
vga_out8 (0x3d5, par->CR68, par);
|
||||
vga_out8 (0x3d5, reg->CR68, par);
|
||||
vga_out8 (0x3d4, 0x69, par);
|
||||
vga_out8 (0x3d5, par->CR69, par);
|
||||
vga_out8 (0x3d5, reg->CR69, par);
|
||||
vga_out8 (0x3d4, 0x6f, par);
|
||||
vga_out8 (0x3d5, par->CR6F, par);
|
||||
vga_out8 (0x3d5, reg->CR6F, par);
|
||||
|
||||
vga_out8 (0x3d4, 0x33, par);
|
||||
vga_out8 (0x3d5, par->CR33, par);
|
||||
vga_out8 (0x3d5, reg->CR33, par);
|
||||
vga_out8 (0x3d4, 0x86, par);
|
||||
vga_out8 (0x3d5, par->CR86, par);
|
||||
vga_out8 (0x3d5, reg->CR86, par);
|
||||
vga_out8 (0x3d4, 0x88, par);
|
||||
vga_out8 (0x3d5, par->CR88, par);
|
||||
vga_out8 (0x3d5, reg->CR88, par);
|
||||
vga_out8 (0x3d4, 0x90, par);
|
||||
vga_out8 (0x3d5, par->CR90, par);
|
||||
vga_out8 (0x3d5, reg->CR90, par);
|
||||
vga_out8 (0x3d4, 0x91, par);
|
||||
vga_out8 (0x3d5, par->CR91, par);
|
||||
vga_out8 (0x3d5, reg->CR91, par);
|
||||
|
||||
if (par->chip == S3_SAVAGE4) {
|
||||
vga_out8 (0x3d4, 0xb0, par);
|
||||
vga_out8 (0x3d5, par->CRB0, par);
|
||||
vga_out8 (0x3d5, reg->CRB0, par);
|
||||
}
|
||||
|
||||
vga_out8 (0x3d4, 0x32, par);
|
||||
vga_out8 (0x3d5, par->CR32, par);
|
||||
vga_out8 (0x3d5, reg->CR32, par);
|
||||
|
||||
/* unlock extended seq regs */
|
||||
vga_out8 (0x3c4, 0x08, par);
|
||||
|
|
@ -1225,27 +1227,27 @@ static void savagefb_set_par_int (struct savagefb_par *par)
|
|||
/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
|
||||
* that we should leave the default SR10 and SR11 values there.
|
||||
*/
|
||||
if (par->SR10 != 255) {
|
||||
if (reg->SR10 != 255) {
|
||||
vga_out8 (0x3c4, 0x10, par);
|
||||
vga_out8 (0x3c5, par->SR10, par);
|
||||
vga_out8 (0x3c5, reg->SR10, par);
|
||||
vga_out8 (0x3c4, 0x11, par);
|
||||
vga_out8 (0x3c5, par->SR11, par);
|
||||
vga_out8 (0x3c5, reg->SR11, par);
|
||||
}
|
||||
|
||||
/* restore extended seq regs for dclk */
|
||||
vga_out8 (0x3c4, 0x0e, par);
|
||||
vga_out8 (0x3c5, par->SR0E, par);
|
||||
vga_out8 (0x3c5, reg->SR0E, par);
|
||||
vga_out8 (0x3c4, 0x0f, par);
|
||||
vga_out8 (0x3c5, par->SR0F, par);
|
||||
vga_out8 (0x3c5, reg->SR0F, par);
|
||||
vga_out8 (0x3c4, 0x12, par);
|
||||
vga_out8 (0x3c5, par->SR12, par);
|
||||
vga_out8 (0x3c5, reg->SR12, par);
|
||||
vga_out8 (0x3c4, 0x13, par);
|
||||
vga_out8 (0x3c5, par->SR13, par);
|
||||
vga_out8 (0x3c5, reg->SR13, par);
|
||||
vga_out8 (0x3c4, 0x29, par);
|
||||
vga_out8 (0x3c5, par->SR29, par);
|
||||
vga_out8 (0x3c5, reg->SR29, par);
|
||||
|
||||
vga_out8 (0x3c4, 0x18, par);
|
||||
vga_out8 (0x3c5, par->SR18, par);
|
||||
vga_out8 (0x3c5, reg->SR18, par);
|
||||
|
||||
/* load new m, n pll values for dclk & mclk */
|
||||
vga_out8 (0x3c4, 0x15, par);
|
||||
|
|
@ -1254,18 +1256,18 @@ static void savagefb_set_par_int (struct savagefb_par *par)
|
|||
vga_out8 (0x3c5, tmp | 0x03, par);
|
||||
vga_out8 (0x3c5, tmp | 0x23, par);
|
||||
vga_out8 (0x3c5, tmp | 0x03, par);
|
||||
vga_out8 (0x3c5, par->SR15, par);
|
||||
vga_out8 (0x3c5, reg->SR15, par);
|
||||
udelay (100);
|
||||
|
||||
vga_out8 (0x3c4, 0x30, par);
|
||||
vga_out8 (0x3c5, par->SR30, par);
|
||||
vga_out8 (0x3c5, reg->SR30, par);
|
||||
vga_out8 (0x3c4, 0x08, par);
|
||||
vga_out8 (0x3c5, par->SR08, par);
|
||||
vga_out8 (0x3c5, reg->SR08, par);
|
||||
|
||||
/* now write out cr67 in full, possibly starting STREAMS */
|
||||
VerticalRetraceWait(par);
|
||||
vga_out8 (0x3d4, 0x67, par);
|
||||
vga_out8 (0x3d5, par->CR67, par);
|
||||
vga_out8 (0x3d5, reg->CR67, par);
|
||||
|
||||
vga_out8 (0x3d4, 0x66, par);
|
||||
cr66 = vga_in8 (0x3d5, par);
|
||||
|
|
@ -1276,13 +1278,13 @@ static void savagefb_set_par_int (struct savagefb_par *par)
|
|||
|
||||
if (par->chip != S3_SAVAGE_MX) {
|
||||
VerticalRetraceWait(par);
|
||||
savage_out32 (FIFO_CONTROL_REG, par->MMPR0, par);
|
||||
savage_out32 (FIFO_CONTROL_REG, reg->MMPR0, par);
|
||||
par->SavageWaitIdle (par);
|
||||
savage_out32 (MIU_CONTROL_REG, par->MMPR1, par);
|
||||
savage_out32 (MIU_CONTROL_REG, reg->MMPR1, par);
|
||||
par->SavageWaitIdle (par);
|
||||
savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2, par);
|
||||
savage_out32 (STREAMS_TIMEOUT_REG, reg->MMPR2, par);
|
||||
par->SavageWaitIdle (par);
|
||||
savage_out32 (MISC_TIMEOUT_REG, par->MMPR3, par);
|
||||
savage_out32 (MISC_TIMEOUT_REG, reg->MMPR3, par);
|
||||
}
|
||||
|
||||
vga_out8 (0x3d4, 0x66, par);
|
||||
|
|
@ -1347,7 +1349,7 @@ static int savagefb_set_par (struct fb_info *info)
|
|||
int err;
|
||||
|
||||
DBG("savagefb_set_par");
|
||||
err = savagefb_decode_var (var, par);
|
||||
err = savagefb_decode_var (var, par, &par->state);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
@ -1366,7 +1368,7 @@ static int savagefb_set_par (struct fb_info *info)
|
|||
par->maxClock = par->dacSpeedBpp;
|
||||
par->minClock = 10000;
|
||||
|
||||
savagefb_set_par_int (par);
|
||||
savagefb_set_par_int (par, &par->state);
|
||||
fb_set_cmap (&info->cmap, info);
|
||||
savagefb_set_fix(info);
|
||||
savagefb_set_clip(info);
|
||||
|
|
@ -1824,7 +1826,8 @@ static int savage_init_hw (struct savagefb_par *par)
|
|||
par->display_type = DISP_CRT;
|
||||
}
|
||||
|
||||
savage_get_default_par (par);
|
||||
savage_get_default_par (par, &par->state);
|
||||
par->save = par->state;
|
||||
|
||||
if( S3_SAVAGE4_SERIES(par->chip) ) {
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in a new issue