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[TG3]: add basic bcm5752 support
Add ASIC_REV_5752 definition. Track-down all references to ASIC_REV_5750 and mirror them with references to the newly defined ASIC_REV_5752. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
John W. Linville
David S. Miller
parent
ebc37b6116
commit
2052da9460
2 changed files with 43 additions and 21 deletions
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@ -86,7 +86,8 @@
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#define TG3_MIN_MTU 60
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#define TG3_MAX_MTU(tp) \
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((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) ? 9000 : 1500)
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && \
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) ? 9000 : 1500)
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/* These numbers seem to be hard coded in the NIC firmware somehow.
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* You can't change the ring sizes, but you can change where you place
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@ -861,7 +862,8 @@ out:
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/* Cannot do read-modify-write on 5401 */
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
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} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
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u32 phy_reg;
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/* Set bit 14 with read-modify-write to preserve other bits */
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@ -874,7 +876,8 @@ out:
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* jumbo frames transmission.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
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u32 phy_reg;
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if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
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@ -1068,7 +1071,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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mac_mode = MAC_MODE_PORT_MODE_TBI;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
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tw32(MAC_LED_CTRL, tp->led_ctrl);
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if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
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@ -3967,7 +3971,8 @@ static int tg3_chip_reset(struct tg3 *tp)
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
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if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
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tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
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}
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}
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@ -5041,7 +5046,8 @@ static int tg3_reset_hw(struct tg3 *tp)
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tw32(GRC_MISC_CFG, val);
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/* Initialize MBUF/DESC pool. */
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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/* Do nothing. */
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} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
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tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
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@ -5240,7 +5246,8 @@ static int tg3_reset_hw(struct tg3 *tp)
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rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
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tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
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if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
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(tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
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@ -5355,7 +5362,8 @@ static int tg3_reset_hw(struct tg3 *tp)
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
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tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
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if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
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(tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
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@ -7028,7 +7036,8 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
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tw32(NVRAM_CFG1, nvcfg1);
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
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case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
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tp->nvram_jedecnum = JEDEC_ATMEL;
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@ -7093,7 +7102,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
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tp->tg3_flags |= TG3_FLAG_NVRAM;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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@ -7102,7 +7112,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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tg3_get_nvram_info(tp);
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tg3_get_nvram_size(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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@ -7195,7 +7206,8 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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tg3_nvram_lock(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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@ -7210,7 +7222,8 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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tg3_nvram_unlock(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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@ -7438,7 +7451,8 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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tg3_nvram_lock(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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@ -7463,7 +7477,8 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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grc_mode = tr32(GRC_MODE);
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tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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u32 nvaccess = tr32(NVRAM_ACCESS);
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tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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@ -7581,7 +7596,8 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
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} else
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eeprom_phy_id = 0;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
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led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
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SHASTA_EXT_LED_MODE_MASK);
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} else
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@ -7634,7 +7650,8 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
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if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
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tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
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}
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if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
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@ -7932,10 +7949,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752))
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tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
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if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
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@ -8066,7 +8085,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
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/* Only 5701 and later support tagged irq status mode.
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@ -8462,7 +8482,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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tp->dma_rwctrl |= 0x00180000;
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} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tp->dma_rwctrl |= 0x003f0000;
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else
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tp->dma_rwctrl |= 0x003f000f;
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@ -132,6 +132,7 @@
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#define ASIC_REV_5704 0x02
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#define ASIC_REV_5705 0x03
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#define ASIC_REV_5750 0x04
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#define ASIC_REV_5752 0x05
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#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
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#define CHIPREV_5700_AX 0x70
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#define CHIPREV_5700_BX 0x71
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