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sh: Clock framework tidying.
This syncs up the SH clock framework with the linux/clk.h API, for which there were only some minor changes required, namely the clk_get() dev_id and subsequent callsites. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
e74b56800e
commit
1d118562c2
9 changed files with 38 additions and 23 deletions
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@ -5,9 +5,11 @@
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*
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* This clock framework is derived from the OMAP version by:
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*
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* Copyright (C) 2004 Nokia Corporation
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* Copyright (C) 2004 - 2005 Nokia Corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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*
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* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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@ -20,6 +22,7 @@
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#include <linux/kref.h>
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#include <linux/seq_file.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <asm/clock.h>
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#include <asm/timer.h>
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@ -195,17 +198,37 @@ void clk_recalc_rate(struct clk *clk)
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propagate_rate(clk);
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}
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struct clk *clk_get(const char *id)
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/*
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* Returns a clock. Note that we first try to use device id on the bus
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* and clock name. If this fails, we try to use clock name only.
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*/
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struct clk *clk_get(struct device *dev, const char *id)
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{
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struct clk *p, *clk = ERR_PTR(-ENOENT);
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int idno;
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if (dev == NULL || dev->bus != &platform_bus_type)
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idno = -1;
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else
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idno = to_platform_device(dev)->id;
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mutex_lock(&clock_list_sem);
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list_for_each_entry(p, &clock_list, node) {
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if (p->id == idno &&
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strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
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clk = p;
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goto found;
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}
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}
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list_for_each_entry(p, &clock_list, node) {
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if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
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clk = p;
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break;
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}
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}
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found:
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mutex_unlock(&clock_list_sem);
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return clk;
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@ -24,7 +24,7 @@ static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
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static void set_bus_parent(struct clk *clk)
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{
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struct clk *bus_clk = clk_get("bus_clk");
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struct clk *bus_clk = clk_get(NULL, "bus_clk");
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clk->parent = bus_clk;
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clk_put(bus_clk);
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}
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@ -97,7 +97,7 @@ static void shoc_clk_recalc(struct clk *clk)
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static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *bclk = clk_get("bus_clk");
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struct clk *bclk = clk_get(NULL, "bus_clk");
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unsigned long bclk_rate = clk_get_rate(bclk);
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clk_put(bclk);
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@ -151,7 +151,7 @@ static struct clk *sh4202_onchip_clocks[] = {
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static int __init sh4202_clk_init(void)
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{
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struct clk *clk = clk_get("master_clk");
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struct clk *clk = clk_get(NULL, "master_clk");
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int i;
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for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
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@ -98,7 +98,7 @@ static struct clk *sh7780_onchip_clocks[] = {
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static int __init sh7780_clk_init(void)
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{
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struct clk *clk = clk_get("master_clk");
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struct clk *clk = clk_get(NULL, "master_clk");
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int i;
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for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
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@ -124,7 +124,7 @@ static void cmt_clk_init(struct clk *clk)
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u8 divisor = CMT_CMCSR_INIT & 0x3;
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ctrl_inw(CMT_CMCSR_0);
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ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
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clk->parent = clk_get("module_clk");
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clk->parent = clk_get(NULL, "module_clk");
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clk->rate = clk->parent->rate / (8 << (divisor << 1));
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}
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@ -164,7 +164,7 @@ static int cmt_timer_init(void)
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setup_irq(CONFIG_SH_TIMER_IRQ, &cmt_irq);
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cmt0_clk.parent = clk_get("module_clk");
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cmt0_clk.parent = clk_get(NULL, "module_clk");
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cmt_timer_stop();
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@ -161,7 +161,7 @@ static int mtu2_timer_init(void)
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setup_irq(CONFIG_SH_TIMER_IRQ, &mtu2_irq);
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mtu2_clk1.parent = clk_get("module_clk");
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mtu2_clk1.parent = clk_get(NULL, "module_clk");
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ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
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@ -144,7 +144,7 @@ static int tmu_timer_init(void)
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setup_irq(CONFIG_SH_TIMER_IRQ, &tmu_irq);
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tmu0_clk.parent = clk_get("module_clk");
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tmu0_clk.parent = clk_get(NULL, "module_clk");
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/* Start TMU0 */
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tmu_timer_stop();
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@ -775,7 +775,7 @@ static int sci_notifier(struct notifier_block *self,
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*
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* Clean this up later..
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*/
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clk = clk_get("module_clk");
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clk = clk_get(NULL, "module_clk");
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port->uartclk = clk_get_rate(clk) * 16;
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clk_put(clk);
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}
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@ -960,7 +960,7 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
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default:
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{
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#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
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struct clk *clk = clk_get("module_clk");
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struct clk *clk = clk_get(NULL, "module_clk");
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t = SCBRR_VALUE(baud, clk_get_rate(clk));
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clk_put(clk);
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#else
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@ -1128,7 +1128,7 @@ static void __init sci_init_ports(void)
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* XXX: We should use a proper SCI/SCIF clock
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*/
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{
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struct clk *clk = clk_get("module_clk");
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struct clk *clk = clk_get(NULL, "module_clk");
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sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
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clk_put(clk);
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}
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@ -4,6 +4,7 @@
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#include <linux/kref.h>
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#include <linux/list.h>
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#include <linux/seq_file.h>
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#include <linux/clk.h>
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struct clk;
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@ -18,7 +19,7 @@ struct clk_ops {
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struct clk {
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struct list_head node;
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const char *name;
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int id;
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struct module *owner;
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struct clk *parent;
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int clk_init(void);
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int __clk_enable(struct clk *);
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int clk_enable(struct clk *);
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void __clk_disable(struct clk *);
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void clk_disable(struct clk *);
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int clk_set_rate(struct clk *, unsigned long rate);
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unsigned long clk_get_rate(struct clk *);
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void clk_recalc_rate(struct clk *);
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struct clk *clk_get(const char *id);
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void clk_put(struct clk *);
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int clk_register(struct clk *);
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void clk_unregister(struct clk *);
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int show_clocks(struct seq_file *m);
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#endif /* __ASM_SH_CLOCK_H */
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