mirror of
https://github.com/adulau/aha.git
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: amd64_edac: beef up DRAM error injection amd64_edac: fix DRAM base and limit extraction amd64_edac: fix chip select handling amd64_edac: simple fix to allow reporting of CECC errors amd64_edac: fix K8 intlv_sel check amd64_edac: fix interleave enable tests amd64_edac: fix DRAM base and limit address extraction amd64_edac: fix driver instance lookup table allocation
This commit is contained in:
Linus Torvalds
commit
1bfd16a657
3 changed files with 101 additions and 75 deletions
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@ -15,8 +15,8 @@ module_param(ecc_enable_override, int, 0644);
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/* Lookup table for all possible MC control instances */
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struct amd64_pvt;
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static struct mem_ctl_info *mci_lookup[MAX_NUMNODES];
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static struct amd64_pvt *pvt_lookup[MAX_NUMNODES];
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static struct mem_ctl_info *mci_lookup[EDAC_MAX_NUMNODES];
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static struct amd64_pvt *pvt_lookup[EDAC_MAX_NUMNODES];
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/*
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* See F2x80 for K8 and F2x[1,0]80 for Fam10 and later. The table below is only
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@ -189,7 +189,10 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
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/* Map from a CSROW entry to the mask entry that operates on it */
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static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)
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{
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return csrow >> (pvt->num_dcsm >> 3);
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if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F)
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return csrow;
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else
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return csrow >> 1;
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}
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/* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
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@ -279,29 +282,26 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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intlv_en = pvt->dram_IntlvEn[0];
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if (intlv_en == 0) {
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for (node_id = 0; ; ) {
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for (node_id = 0; node_id < DRAM_REG_COUNT; node_id++) {
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if (amd64_base_limit_match(pvt, sys_addr, node_id))
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break;
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if (++node_id >= DRAM_REG_COUNT)
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goto err_no_match;
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goto found;
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}
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goto found;
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goto err_no_match;
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}
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if (unlikely((intlv_en != (0x01 << 8)) &&
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(intlv_en != (0x03 << 8)) &&
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(intlv_en != (0x07 << 8)))) {
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if (unlikely((intlv_en != 0x01) &&
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(intlv_en != 0x03) &&
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(intlv_en != 0x07))) {
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amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from "
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"IntlvEn field of DRAM Base Register for node 0: "
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"This probably indicates a BIOS bug.\n", intlv_en);
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"this probably indicates a BIOS bug.\n", intlv_en);
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return NULL;
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}
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bits = (((u32) sys_addr) >> 12) & intlv_en;
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for (node_id = 0; ; ) {
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if ((pvt->dram_limit[node_id] & intlv_en) == bits)
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if ((pvt->dram_IntlvSel[node_id] & intlv_en) == bits)
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break; /* intlv_sel field matches */
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if (++node_id >= DRAM_REG_COUNT)
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@ -311,10 +311,10 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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/* sanity test for sys_addr */
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if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
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amd64_printk(KERN_WARNING,
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"%s(): sys_addr 0x%lx falls outside base/limit "
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"address range for node %d with node interleaving "
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"enabled.\n", __func__, (unsigned long)sys_addr,
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node_id);
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"%s(): sys_addr 0x%llx falls outside base/limit "
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"address range for node %d with node interleaving "
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"enabled.\n",
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__func__, sys_addr, node_id);
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return NULL;
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}
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@ -377,7 +377,7 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
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* base/mask register pair, test the condition shown near the start of
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* section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
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*/
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for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {
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for (csrow = 0; csrow < pvt->cs_count; csrow++) {
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/* This DRAM chip select is disabled on this node */
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if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)
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@ -734,7 +734,7 @@ static void find_csrow_limits(struct mem_ctl_info *mci, int csrow,
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u64 base, mask;
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pvt = mci->pvt_info;
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BUG_ON((csrow < 0) || (csrow >= CHIPSELECT_COUNT));
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BUG_ON((csrow < 0) || (csrow >= pvt->cs_count));
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base = base_from_dct_base(pvt, csrow);
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mask = mask_from_dct_mask(pvt, csrow);
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@ -962,35 +962,27 @@ err_reg:
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*/
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static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt)
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{
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if (pvt->ext_model >= OPTERON_CPU_REV_F) {
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if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F) {
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pvt->dcsb_base = REV_E_DCSB_BASE_BITS;
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pvt->dcsm_mask = REV_E_DCSM_MASK_BITS;
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pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS;
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pvt->dcs_shift = REV_E_DCS_SHIFT;
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pvt->cs_count = 8;
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pvt->num_dcsm = 8;
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} else {
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pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS;
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pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS;
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pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS;
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pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT;
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switch (boot_cpu_data.x86) {
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case 0xf:
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pvt->num_dcsm = REV_F_DCSM_COUNT;
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break;
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case 0x10:
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pvt->num_dcsm = F10_DCSM_COUNT;
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break;
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case 0x11:
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pvt->num_dcsm = F11_DCSM_COUNT;
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break;
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default:
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amd64_printk(KERN_ERR, "Unsupported family!\n");
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break;
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if (boot_cpu_data.x86 == 0x11) {
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pvt->cs_count = 4;
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pvt->num_dcsm = 2;
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} else {
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pvt->cs_count = 8;
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pvt->num_dcsm = 4;
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}
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} else {
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pvt->dcsb_base = REV_E_DCSB_BASE_BITS;
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pvt->dcsm_mask = REV_E_DCSM_MASK_BITS;
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pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS;
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pvt->dcs_shift = REV_E_DCS_SHIFT;
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pvt->num_dcsm = REV_E_DCSM_COUNT;
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}
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}
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@ -1003,7 +995,7 @@ static void amd64_read_dct_base_mask(struct amd64_pvt *pvt)
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amd64_set_dct_base_and_mask(pvt);
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for (cs = 0; cs < CHIPSELECT_COUNT; cs++) {
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for (cs = 0; cs < pvt->cs_count; cs++) {
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reg = K8_DCSB0 + (cs * 4);
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err = pci_read_config_dword(pvt->dram_f2_ctl, reg,
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&pvt->dcsb0[cs]);
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@ -1130,7 +1122,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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debugf0("Reading K8_DRAM_BASE_LOW failed\n");
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/* Extract parts into separate data entries */
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pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
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pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 24;
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pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
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pvt->dram_rw_en[dram] = (low & 0x3);
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@ -1143,7 +1135,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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* Extract parts into separate data entries. Limit is the HIGHEST memory
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* location of the region, so lower 24 bits need to be all ones
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*/
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pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
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pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 24) | 0x00FFFFFF;
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pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
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pvt->dram_DstNode[dram] = (low & 0x7);
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}
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@ -1193,7 +1185,7 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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* different from the node that detected the error.
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*/
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src_mci = find_mc_by_sys_addr(mci, SystemAddress);
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if (src_mci) {
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if (!src_mci) {
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amd64_mc_printk(mci, KERN_ERR,
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"failed to map error address 0x%lx to a node\n",
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(unsigned long)SystemAddress);
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@ -1376,8 +1368,8 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
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pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) |
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((u64) low_base & 0xFFFF0000))) << 8;
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pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
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(((u64)low_base & 0xFFFF0000) << 24);
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low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
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high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
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@ -1398,9 +1390,9 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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* Extract address values and form a LIMIT address. Limit is the HIGHEST
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* memory location of the region, so low 24 bits need to be all ones.
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*/
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low_limit |= 0x0000FFFF;
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pvt->dram_limit[dram] =
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((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF);
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pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
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(((u64) low_limit & 0xFFFF0000) << 24) |
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0x00FFFFFF;
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}
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static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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@ -1566,7 +1558,7 @@ static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs)
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debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs);
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for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {
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for (csrow = 0; csrow < pvt->cs_count; csrow++) {
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cs_base = amd64_get_dct_base(pvt, cs, csrow);
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if (!(cs_base & K8_DCSB_CS_ENABLE))
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@ -2497,7 +2489,7 @@ err_reg:
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* NOTE: CPU Revision Dependent code
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*
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* Input:
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* @csrow_nr ChipSelect Row Number (0..CHIPSELECT_COUNT-1)
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* @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1)
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* k8 private pointer to -->
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* DRAM Bank Address mapping register
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* node_id
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@ -2577,7 +2569,7 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
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(pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"
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);
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for (i = 0; i < CHIPSELECT_COUNT; i++) {
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for (i = 0; i < pvt->cs_count; i++) {
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csrow = &mci->csrows[i];
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if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) {
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@ -2988,7 +2980,7 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
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goto err_exit;
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ret = -ENOMEM;
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mci = edac_mc_alloc(0, CHIPSELECT_COUNT, pvt->channel_count, node_id);
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mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id);
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if (!mci)
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goto err_exit;
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@ -132,6 +132,8 @@
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#define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__
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#define EDAC_MOD_STR "amd64_edac"
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#define EDAC_MAX_NUMNODES 8
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/* Extended Model from CPUID, for CPU Revision numbers */
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#define OPTERON_CPU_LE_REV_C 0
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#define OPTERON_CPU_REV_D 1
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@ -142,7 +144,7 @@
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#define OPTERON_CPU_REV_FA 5
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/* Hardware limit on ChipSelect rows per MC and processors per system */
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#define CHIPSELECT_COUNT 8
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#define MAX_CS_COUNT 8
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#define DRAM_REG_COUNT 8
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@ -193,7 +195,6 @@
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*/
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#define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL)
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#define REV_E_DCS_SHIFT 4
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#define REV_E_DCSM_COUNT 8
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#define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL)
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#define REV_F_F1Xh_DCS_SHIFT 8
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@ -204,9 +205,6 @@
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*/
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#define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL)
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#define REV_F_DCS_SHIFT 8
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#define REV_F_DCSM_COUNT 4
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#define F10_DCSM_COUNT 4
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#define F11_DCSM_COUNT 2
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|
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/* DRAM CS Mask Registers */
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#define K8_DCSM0 0x60
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@ -374,13 +372,11 @@ enum {
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|
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#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
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(BIT(((word) & 0xF) + 20) | \
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BIT(17) | \
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((bits) & 0xF))
|
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BIT(17) | bits)
|
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|
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#define SET_NB_DRAM_INJECTION_READ(word, bits) \
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(BIT(((word) & 0xF) + 20) | \
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BIT(16) | \
|
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((bits) & 0xF))
|
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BIT(16) | bits)
|
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|
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#define K8_NBCAP 0xE8
|
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#define K8_NBCAP_CORES (BIT(12)|BIT(13))
|
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|
|
@ -445,12 +441,12 @@ struct amd64_pvt {
|
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u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
|
||||
|
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/* DRAM CS Base Address Registers F2x[1,0][5C:40] */
|
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u32 dcsb0[CHIPSELECT_COUNT];
|
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u32 dcsb1[CHIPSELECT_COUNT];
|
||||
u32 dcsb0[MAX_CS_COUNT];
|
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u32 dcsb1[MAX_CS_COUNT];
|
||||
|
||||
/* DRAM CS Mask Registers F2x[1,0][6C:60] */
|
||||
u32 dcsm0[CHIPSELECT_COUNT];
|
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u32 dcsm1[CHIPSELECT_COUNT];
|
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u32 dcsm0[MAX_CS_COUNT];
|
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u32 dcsm1[MAX_CS_COUNT];
|
||||
|
||||
/*
|
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* Decoded parts of DRAM BASE and LIMIT Registers
|
||||
|
|
@ -470,6 +466,7 @@ struct amd64_pvt {
|
|||
*/
|
||||
u32 dcsb_base; /* DCSB base bits */
|
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u32 dcsm_mask; /* DCSM mask bits */
|
||||
u32 cs_count; /* num chip selects (== num DCSB registers) */
|
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u32 num_dcsm; /* Number of DCSM registers */
|
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u32 dcs_mask_notused; /* DCSM notused mask bits */
|
||||
u32 dcs_shift; /* DCSB and DCSM shift value */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
#include "amd64_edac.h"
|
||||
|
||||
static ssize_t amd64_inject_section_show(struct mem_ctl_info *mci, char *buf)
|
||||
{
|
||||
struct amd64_pvt *pvt = mci->pvt_info;
|
||||
return sprintf(buf, "0x%x\n", pvt->injection.section);
|
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}
|
||||
|
||||
/*
|
||||
* store error injection section value which refers to one of 4 16-byte sections
|
||||
* within a 64-byte cacheline
|
||||
|
|
@ -15,12 +21,26 @@ static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
|
|||
|
||||
ret = strict_strtoul(data, 10, &value);
|
||||
if (ret != -EINVAL) {
|
||||
|
||||
if (value > 3) {
|
||||
amd64_printk(KERN_WARNING,
|
||||
"%s: invalid section 0x%lx\n",
|
||||
__func__, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pvt->injection.section = (u32) value;
|
||||
return count;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t amd64_inject_word_show(struct mem_ctl_info *mci, char *buf)
|
||||
{
|
||||
struct amd64_pvt *pvt = mci->pvt_info;
|
||||
return sprintf(buf, "0x%x\n", pvt->injection.word);
|
||||
}
|
||||
|
||||
/*
|
||||
* store error injection word value which refers to one of 9 16-bit word of the
|
||||
* 16-byte (128-bit + ECC bits) section
|
||||
|
|
@ -37,14 +57,25 @@ static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
|
|||
ret = strict_strtoul(data, 10, &value);
|
||||
if (ret != -EINVAL) {
|
||||
|
||||
value = (value <= 8) ? value : 0;
|
||||
pvt->injection.word = (u32) value;
|
||||
if (value > 8) {
|
||||
amd64_printk(KERN_WARNING,
|
||||
"%s: invalid word 0x%lx\n",
|
||||
__func__, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pvt->injection.word = (u32) value;
|
||||
return count;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t amd64_inject_ecc_vector_show(struct mem_ctl_info *mci, char *buf)
|
||||
{
|
||||
struct amd64_pvt *pvt = mci->pvt_info;
|
||||
return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
|
||||
}
|
||||
|
||||
/*
|
||||
* store 16 bit error injection vector which enables injecting errors to the
|
||||
* corresponding bit within the error injection word above. When used during a
|
||||
|
|
@ -60,8 +91,14 @@ static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci,
|
|||
ret = strict_strtoul(data, 16, &value);
|
||||
if (ret != -EINVAL) {
|
||||
|
||||
pvt->injection.bit_map = (u32) value & 0xFFFF;
|
||||
if (value & 0xFFFF0000) {
|
||||
amd64_printk(KERN_WARNING,
|
||||
"%s: invalid EccVector: 0x%lx\n",
|
||||
__func__, value);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pvt->injection.bit_map = (u32) value;
|
||||
return count;
|
||||
}
|
||||
return ret;
|
||||
|
|
@ -147,7 +184,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
|
|||
.name = "inject_section",
|
||||
.mode = (S_IRUGO | S_IWUSR)
|
||||
},
|
||||
.show = NULL,
|
||||
.show = amd64_inject_section_show,
|
||||
.store = amd64_inject_section_store,
|
||||
},
|
||||
{
|
||||
|
|
@ -155,7 +192,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
|
|||
.name = "inject_word",
|
||||
.mode = (S_IRUGO | S_IWUSR)
|
||||
},
|
||||
.show = NULL,
|
||||
.show = amd64_inject_word_show,
|
||||
.store = amd64_inject_word_store,
|
||||
},
|
||||
{
|
||||
|
|
@ -163,7 +200,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
|
|||
.name = "inject_ecc_vector",
|
||||
.mode = (S_IRUGO | S_IWUSR)
|
||||
},
|
||||
.show = NULL,
|
||||
.show = amd64_inject_ecc_vector_show,
|
||||
.store = amd64_inject_ecc_vector_store,
|
||||
},
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue