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KVM: Keep track of missed timer irq injections
APIC timer IRQ is set every time when a certain period expires at host time, but the guest may be descheduled at that time and thus the irq be overwritten by later fire. This patch keep track of firing irq numbers and decrease only when the IRQ is injected to guest or buffered in APIC. Signed-off-by: Yaozu (Eddie) Dong <Eddie.Dong@intel.com> Signed-off-by: Qing He <qing.he@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
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parent
6e5d865c0b
commit
1b9778dae7
6 changed files with 69 additions and 25 deletions
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@ -78,3 +78,16 @@ void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
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smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0, 0);
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}
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void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu)
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{
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kvm_inject_apic_timer_irqs(vcpu);
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/* TODO: PIT, RTC etc. */
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}
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EXPORT_SYMBOL_GPL(kvm_inject_pending_timer_irqs);
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void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
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{
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kvm_apic_timer_intr_post(vcpu, vec);
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/* TODO: PIT, RTC etc. */
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}
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EXPORT_SYMBOL_GPL(kvm_timer_intr_post);
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@ -154,5 +154,9 @@ int kvm_ioapic_init(struct kvm *kvm);
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void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
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int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
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void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
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void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
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void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu);
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void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu);
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#endif
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@ -283,6 +283,8 @@ EXPORT_SYMBOL_GPL(kvm_vcpu_init);
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void kvm_vcpu_uninit(struct kvm_vcpu *vcpu)
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{
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kvm_mmu_destroy(vcpu);
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if (vcpu->apic)
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hrtimer_cancel(&vcpu->apic->timer.dev);
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kvm_free_apic(vcpu->apic);
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free_page((unsigned long)vcpu->pio_data);
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free_page((unsigned long)vcpu->run);
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@ -313,6 +313,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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int vector, int level, int trig_mode)
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{
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int result = 0;
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int orig_irr;
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switch (delivery_mode) {
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case APIC_DM_FIXED:
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@ -321,7 +322,8 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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if (unlikely(!apic_enabled(apic)))
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break;
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if (apic_test_and_set_irr(vector, apic) && trig_mode) {
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orig_irr = apic_test_and_set_irr(vector, apic);
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if (orig_irr && trig_mode) {
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apic_debug("level trig mode repeatedly for vector %d",
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vector);
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break;
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@ -335,7 +337,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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kvm_vcpu_kick(apic->vcpu);
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result = 1;
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result = (orig_irr == 0);
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break;
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case APIC_DM_REMRD:
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@ -831,38 +833,33 @@ EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
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* timer interface
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*----------------------------------------------------------------------
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*/
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/* TODO: make sure __apic_timer_fn runs in current pCPU */
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static int __apic_timer_fn(struct kvm_lapic *apic)
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{
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u32 vector;
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int result = 0;
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wait_queue_head_t *q = &apic->vcpu->wq;
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if (unlikely(!apic_enabled(apic) ||
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!apic_lvt_enabled(apic, APIC_LVTT))) {
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apic_debug("%s: time interrupt although apic is down\n",
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__FUNCTION__);
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return 0;
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}
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vector = apic_lvt_vector(apic, APIC_LVTT);
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apic->timer.last_update = apic->timer.dev.expires;
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atomic_inc(&apic->timer.pending);
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__apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
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if (waitqueue_active(q))
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wake_up_interruptible(q);
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if (apic_lvtt_period(apic)) {
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u32 offset;
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u32 tmict = apic_get_reg(apic, APIC_TMICT);
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offset = APIC_BUS_CYCLE_NS * apic->timer.divide_count * tmict;
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result = 1;
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apic->timer.dev.expires = ktime_add_ns(
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apic->timer.dev.expires,
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apic->timer.period);
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}
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return result;
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}
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static int __inject_apic_timer_irq(struct kvm_lapic *apic)
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{
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int vector;
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vector = apic_lvt_vector(apic, APIC_LVTT);
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return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
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}
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static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
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{
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struct kvm_lapic *apic;
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@ -935,6 +932,27 @@ int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
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return highest_irr;
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}
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void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
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{
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struct kvm_lapic *apic = vcpu->apic;
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if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
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atomic_read(&apic->timer.pending) > 0) {
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if (__inject_apic_timer_irq(apic))
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atomic_dec(&apic->timer.pending);
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}
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}
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void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
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{
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struct kvm_lapic *apic = vcpu->apic;
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if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
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apic->timer.last_update = ktime_add_ns(
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apic->timer.last_update,
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apic->timer.period);
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}
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int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
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{
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int vector = kvm_apic_has_interrupt(vcpu);
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@ -1331,7 +1331,9 @@ static void svm_intr_assist(struct vcpu_svm *svm)
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{
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struct vmcb *vmcb = svm->vmcb;
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int intr_vector = -1;
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struct kvm_vcpu *vcpu = &svm->vcpu;
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kvm_inject_pending_timer_irqs(vcpu);
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if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
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((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
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intr_vector = vmcb->control.exit_int_info &
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@ -1344,7 +1346,7 @@ static void svm_intr_assist(struct vcpu_svm *svm)
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if (vmcb->control.int_ctl & V_IRQ_MASK)
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return;
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if (!kvm_cpu_has_interrupt(&svm->vcpu))
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if (!kvm_cpu_has_interrupt(vcpu))
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return;
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if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
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@ -1356,8 +1358,9 @@ static void svm_intr_assist(struct vcpu_svm *svm)
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return;
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}
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/* Okay, we can deliver the interrupt: grab it and update PIC state. */
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intr_vector = kvm_cpu_get_interrupt(&svm->vcpu);
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intr_vector = kvm_cpu_get_interrupt(vcpu);
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svm_inject_irq(svm, intr_vector);
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kvm_timer_intr_post(vcpu, intr_vector);
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}
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static void kvm_reput_irq(struct vcpu_svm *svm)
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@ -2151,7 +2151,9 @@ static void vmx_intr_assist(struct kvm_vcpu *vcpu)
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{
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u32 idtv_info_field, intr_info_field;
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int has_ext_irq, interrupt_window_open;
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int vector;
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kvm_inject_pending_timer_irqs(vcpu);
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update_tpr_threshold(vcpu);
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has_ext_irq = kvm_cpu_has_interrupt(vcpu);
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@ -2183,9 +2185,11 @@ static void vmx_intr_assist(struct kvm_vcpu *vcpu)
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interrupt_window_open =
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((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
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(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
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if (interrupt_window_open)
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vmx_inject_irq(vcpu, kvm_cpu_get_interrupt(vcpu));
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else
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if (interrupt_window_open) {
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vector = kvm_cpu_get_interrupt(vcpu);
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vmx_inject_irq(vcpu, vector);
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kvm_timer_intr_post(vcpu, vector);
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} else
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enable_irq_window(vcpu);
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}
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