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trivial: fix typo milisecond/millisecond for documentation and source comments.
Signed-off-by: Martin Olsson <martin@minimum.se> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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8 changed files with 9 additions and 9 deletions
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@ -698,8 +698,8 @@ very often is not. Abundant use of the inline keyword leads to a much bigger
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kernel, which in turn slows the system as a whole down, due to a bigger
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kernel, which in turn slows the system as a whole down, due to a bigger
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icache footprint for the CPU and simply because there is less memory
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icache footprint for the CPU and simply because there is less memory
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available for the pagecache. Just think about it; a pagecache miss causes a
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available for the pagecache. Just think about it; a pagecache miss causes a
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disk seek, which easily takes 5 miliseconds. There are a LOT of cpu cycles
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disk seek, which easily takes 5 milliseconds. There are a LOT of cpu cycles
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that can go into these 5 miliseconds.
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that can go into these 5 milliseconds.
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A reasonable rule of thumb is to not put inline at functions that have more
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A reasonable rule of thumb is to not put inline at functions that have more
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than 3 lines of code in them. An exception to this rule are the cases where
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than 3 lines of code in them. An exception to this rule are the cases where
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@ -577,7 +577,7 @@ static ide_startstop_t ide_transfer_pc(ide_drive_t *drive)
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/*
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/*
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* If necessary schedule the packet transfer to occur 'timeout'
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* If necessary schedule the packet transfer to occur 'timeout'
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* miliseconds later in ide_delayed_transfer_pc() after the
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* milliseconds later in ide_delayed_transfer_pc() after the
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* device says it's ready for a packet.
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* device says it's ready for a packet.
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*/
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*/
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if (drive->atapi_flags & IDE_AFLAG_ZIP_DRIVE) {
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if (drive->atapi_flags & IDE_AFLAG_ZIP_DRIVE) {
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@ -502,7 +502,7 @@ tone_off:
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break;
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break;
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}
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}
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dsp->cmx_delay = (*((int *)data)) << 3;
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dsp->cmx_delay = (*((int *)data)) << 3;
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/* miliseconds to samples */
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/* milliseconds to samples */
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if (dsp->cmx_delay >= (CMX_BUFF_HALF>>1))
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if (dsp->cmx_delay >= (CMX_BUFF_HALF>>1))
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/* clip to half of maximum usable buffer
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/* clip to half of maximum usable buffer
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(half of half buffer) */
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(half of half buffer) */
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@ -514,7 +514,7 @@ enum ipg_regs {
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#define IPG_DMALIST_ALIGN_PAD 0x07
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#define IPG_DMALIST_ALIGN_PAD 0x07
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#define IPG_MULTICAST_HASHTABLE_SIZE 0x40
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#define IPG_MULTICAST_HASHTABLE_SIZE 0x40
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/* Number of miliseconds to wait after issuing a software reset.
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/* Number of milliseconds to wait after issuing a software reset.
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* 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
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* 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
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*/
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*/
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#define IPG_AC_RESETWAIT 0x05
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#define IPG_AC_RESETWAIT 0x05
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@ -116,7 +116,7 @@ static void zfcp_wka_port_put(struct zfcp_wka_port *wka_port)
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{
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{
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if (atomic_dec_return(&wka_port->refcount) != 0)
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if (atomic_dec_return(&wka_port->refcount) != 0)
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return;
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return;
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/* wait 10 miliseconds, other reqs might pop in */
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/* wait 10 milliseconds, other reqs might pop in */
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schedule_delayed_work(&wka_port->work, HZ / 100);
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schedule_delayed_work(&wka_port->work, HZ / 100);
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}
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}
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@ -342,7 +342,7 @@ uLONG osdGetThreadID(void);
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/* wakes up the specifed thread */
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/* wakes up the specifed thread */
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void osdWakeThread(uLONG);
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void osdWakeThread(uLONG);
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/* osd sleep for x miliseconds */
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/* osd sleep for x milliseconds */
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void osdSleep(uLONG);
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void osdSleep(uLONG);
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#define DPT_THREAD_PRIORITY_LOWEST 0x00
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#define DPT_THREAD_PRIORITY_LOWEST 0x00
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@ -102,7 +102,7 @@ struct edgeport_port {
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__u8 shadow_mcr;
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__u8 shadow_mcr;
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__u8 shadow_lsr;
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__u8 shadow_lsr;
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__u8 lsr_mask;
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__u8 lsr_mask;
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__u32 ump_read_timeout; /* Number of miliseconds the UMP will
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__u32 ump_read_timeout; /* Number of milliseconds the UMP will
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wait without data before completing
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wait without data before completing
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a read short */
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a read short */
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int baud_rate;
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int baud_rate;
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@ -367,7 +367,7 @@ static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *x
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unsigned int port;
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unsigned int port;
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const unsigned char *image;
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const unsigned char *image;
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/* XILINX reset (wait at least 1 milisecond between reset on and off). */
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/* XILINX reset (wait at least 1 millisecond between reset on and off). */
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
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vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
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vx_inl(chip, CNTRL);
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vx_inl(chip, CNTRL);
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msleep(10);
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msleep(10);
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