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[POWERPC] Add ability to 4K kernel to hash in 64K pages
This adds the ability for a kernel compiled with 4K page size to have special slices containing 64K pages and hash the right type of hash PTEs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
parent
d0f13e3c20
commit
16c2d47623
6 changed files with 57 additions and 18 deletions
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@ -546,9 +546,15 @@ config NODES_SPAN_OTHER_NODES
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def_bool y
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depends on NEED_MULTIPLE_NODES
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config PPC_HAS_HASH_64K
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bool
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depends on PPC64
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default n
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config PPC_64K_PAGES
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bool "64k page size"
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depends on PPC64
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select PPC_HAS_HASH_64K
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help
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This option changes the kernel logical page size to 64k. On machines
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without processor support for 64k pages, the kernel will simulate
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@ -615,6 +615,9 @@ htab_pte_insert_failure:
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li r3,-1
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b htab_bail
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#endif /* CONFIG_PPC_64K_PAGES */
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#ifdef CONFIG_PPC_HAS_HASH_64K
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/*****************************************************************************
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* *
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@ -870,7 +873,7 @@ ht64_pte_insert_failure:
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b ht64_bail
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#endif /* CONFIG_PPC_64K_PAGES */
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#endif /* CONFIG_PPC_HAS_HASH_64K */
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/*****************************************************************************
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@ -420,7 +420,7 @@ static void __init htab_finish_init(void)
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extern unsigned int *htab_call_hpte_remove;
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extern unsigned int *htab_call_hpte_updatepp;
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#ifdef CONFIG_PPC_64K_PAGES
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#ifdef CONFIG_PPC_HAS_HASH_64K
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extern unsigned int *ht64_call_hpte_insert1;
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extern unsigned int *ht64_call_hpte_insert2;
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extern unsigned int *ht64_call_hpte_remove;
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@ -648,7 +648,11 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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return 1;
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}
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vsid = get_vsid(mm->context.id, ea);
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#ifdef CONFIG_PPC_MM_SLICES
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psize = get_slice_psize(mm, ea);
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#else
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psize = mm->context.user_psize;
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#endif
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break;
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case VMALLOC_REGION_ID:
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mm = &init_mm;
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@ -678,13 +682,21 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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#ifdef CONFIG_HUGETLB_PAGE
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/* Handle hugepage regions */
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if (HPAGE_SHIFT &&
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unlikely(get_slice_psize(mm, ea) == mmu_huge_psize)) {
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if (HPAGE_SHIFT && psize == mmu_huge_psize) {
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DBG_LOW(" -> huge page !\n");
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return hash_huge_page(mm, access, ea, vsid, local, trap);
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}
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#endif /* CONFIG_HUGETLB_PAGE */
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#ifndef CONFIG_PPC_64K_PAGES
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/* If we use 4K pages and our psize is not 4K, then we are hitting
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* a special driver mapping, we need to align the address before
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* we fetch the PTE
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*/
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if (psize != MMU_PAGE_4K)
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ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
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#endif /* CONFIG_PPC_64K_PAGES */
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/* Get PTE and page size from page tables */
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ptep = find_linux_pte(pgdir, ea);
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if (ptep == NULL || !pte_present(*ptep)) {
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@ -707,9 +719,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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}
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/* Do actual hashing */
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#ifndef CONFIG_PPC_64K_PAGES
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rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
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#else
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#ifdef CONFIG_PPC_64K_PAGES
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/* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
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if (pte_val(*ptep) & _PAGE_4K_PFN) {
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demote_segment_4k(mm, ea);
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@ -751,12 +761,14 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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mmu_psize_defs[mmu_vmalloc_psize].sllp;
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slb_flush_and_rebolt();
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}
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#endif /* CONFIG_PPC_64K_PAGES */
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#ifdef CONFIG_PPC_HAS_HASH_64K
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if (psize == MMU_PAGE_64K)
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rc = __hash_page_64K(ea, access, vsid, ptep, trap, local);
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else
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#endif /* CONFIG_PPC_HAS_HASH_64K */
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rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
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#endif /* CONFIG_PPC_64K_PAGES */
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#ifndef CONFIG_PPC_64K_PAGES
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DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
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@ -812,19 +824,22 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
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/* Get VSID */
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vsid = get_vsid(mm->context.id, ea);
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/* Hash it in */
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/* Hash doesn't like irqs */
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local_irq_save(flags);
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/* Is that local to this CPU ? */
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mask = cpumask_of_cpu(smp_processor_id());
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if (cpus_equal(mm->cpu_vm_mask, mask))
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local = 1;
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#ifndef CONFIG_PPC_64K_PAGES
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__hash_page_4K(ea, access, vsid, ptep, trap, local);
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#else
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/* Hash it in */
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#ifdef CONFIG_PPC_HAS_HASH_64K
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if (mm->context.user_psize == MMU_PAGE_64K)
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__hash_page_64K(ea, access, vsid, ptep, trap, local);
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else
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__hash_page_4K(ea, access, vsid, ptep, trap, local);
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#endif /* CONFIG_PPC_64K_PAGES */
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__hash_page_4K(ea, access, vsid, ptep, trap, local);
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local_irq_restore(flags);
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}
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@ -143,16 +143,22 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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*/
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addr &= PAGE_MASK;
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/* Get page size (maybe move back to caller) */
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/* Get page size (maybe move back to caller).
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*
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* NOTE: when using special 64K mappings in 4K environment like
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* for SPEs, we obtain the page size from the slice, which thus
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* must still exist (and thus the VMA not reused) at the time
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* of this call
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*/
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if (huge) {
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#ifdef CONFIG_HUGETLB_PAGE
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psize = mmu_huge_psize;
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#else
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BUG();
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psize = pte_pagesize_index(pte); /* shutup gcc */
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psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
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#endif
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} else
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psize = pte_pagesize_index(pte);
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psize = pte_pagesize_index(mm, addr, pte);
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/* Build full vaddr */
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if (!is_kernel_addr(addr)) {
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@ -80,7 +80,11 @@
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#define pte_iterate_hashed_end() } while(0)
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#define pte_pagesize_index(pte) MMU_PAGE_4K
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#ifdef CONFIG_PPC_HAS_HASH_64K
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#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
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#else
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#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
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#endif
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/*
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* 4-level page tables related bits
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@ -35,6 +35,11 @@
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#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
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#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
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#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
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/* Note the full page bits must be in the same location as for normal
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* 4k pages as the same asssembly will be used to insert 64K pages
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* wether the kernel has CONFIG_PPC_64K_PAGES or not
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*/
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#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
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#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
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@ -88,7 +93,7 @@
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#define pte_iterate_hashed_end() } while(0); } } while(0)
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#define pte_pagesize_index(pte) \
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#define pte_pagesize_index(mm, addr, pte) \
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(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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