mirror of
https://github.com/adulau/aha.git
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Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-mmc
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-mmc: [MMC] sdhci: version bump sdhci [MMC] sdhci: support controller specific quirks [MMC] sdhci: more DMA capabilities tests [MMC] sdhci: reset sdhci controller early [MMC] sdhci: check controller version [MMC] sdhci: check only relevant inhibit bits [MMC] sdhci: Test for invalid block size [MMC] sdhci: Avoid sdhci DMA boundaries [MMC] Fix sdhci PIO routines [MMC] sdhci: fix interrupt handling [MMC] sdhci: correct register order [MMC] sdhci: proper timeout handling [MMC] sdhci: fix sdhci reset timeout [MMC] sdhci: fix timeout loops in sdhci [MMC] sdhci: support for multiple voltages [MMC] sdhci: print device id [MMC] sdhci: check SDHCI base clock
This commit is contained in:
Linus Torvalds
commit
168d04b3b4
2 changed files with 411 additions and 172 deletions
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@ -8,12 +8,6 @@
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* published by the Free Software Foundation.
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*/
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/*
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* Note that PIO transfer is rather crappy atm. The buffer full/empty
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* interrupts aren't reliable so we currently transfer the entire buffer
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* directly. Patches to solve the problem are welcome.
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*/
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <linux/pci.h>
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@ -27,13 +21,17 @@
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#include "sdhci.h"
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#define DRIVER_NAME "sdhci"
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#define DRIVER_VERSION "0.11"
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#define DRIVER_VERSION "0.12"
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#define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
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#define DBG(f, x...) \
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pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
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static unsigned int debug_nodma = 0;
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static unsigned int debug_forcedma = 0;
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static unsigned int debug_quirks = 0;
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static const struct pci_device_id pci_ids[] __devinitdata = {
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/* handle any SD host controller */
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{PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
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@ -94,12 +92,27 @@ static void sdhci_dumpregs(struct sdhci_host *host)
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static void sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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unsigned long timeout;
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writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
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if (mask & SDHCI_RESET_ALL) {
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if (mask & SDHCI_RESET_ALL)
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host->clock = 0;
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mdelay(50);
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/* Wait max 100 ms */
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timeout = 100;
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/* hw clears the bit when it's done */
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while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
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if (timeout == 0) {
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printk(KERN_ERR "%s: Reset 0x%x never completed. "
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"Please report this to " BUGMAIL ".\n",
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mmc_hostname(host->mmc), (int)mask);
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sdhci_dumpregs(host);
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return;
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}
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timeout--;
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mdelay(1);
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}
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}
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@ -109,13 +122,15 @@ static void sdhci_init(struct sdhci_host *host)
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sdhci_reset(host, SDHCI_RESET_ALL);
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intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
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intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
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SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
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SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
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SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
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SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
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writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
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writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
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/* This is unknown magic. */
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writeb(0xE, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
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}
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static void sdhci_activate_led(struct sdhci_host *host)
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@ -172,79 +187,46 @@ static inline int sdhci_next_sg(struct sdhci_host* host)
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return host->num_sg;
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}
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static void sdhci_transfer_pio(struct sdhci_host *host)
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static void sdhci_read_block_pio(struct sdhci_host *host)
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{
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int blksize, chunk_remain;
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u32 data;
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char *buffer;
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u32 mask;
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int bytes, size;
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unsigned long max_jiffies;
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int size;
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BUG_ON(!host->data);
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DBG("PIO reading\n");
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if (host->num_sg == 0)
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return;
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bytes = 0;
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if (host->data->flags & MMC_DATA_READ)
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mask = SDHCI_DATA_AVAILABLE;
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else
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mask = SDHCI_SPACE_AVAILABLE;
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blksize = host->data->blksz;
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chunk_remain = 0;
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data = 0;
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buffer = sdhci_kmap_sg(host) + host->offset;
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/* Transfer shouldn't take more than 5 s */
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max_jiffies = jiffies + HZ * 5;
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while (host->size > 0) {
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if (time_after(jiffies, max_jiffies)) {
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printk(KERN_ERR "%s: PIO transfer stalled. "
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"Please report this to "
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BUGMAIL ".\n", mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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sdhci_kunmap_sg(host);
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host->data->error = MMC_ERR_FAILED;
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sdhci_finish_data(host);
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return;
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while (blksize) {
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if (chunk_remain == 0) {
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data = readl(host->ioaddr + SDHCI_BUFFER);
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chunk_remain = min(blksize, 4);
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}
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if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
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continue;
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size = min(host->size, host->remain);
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size = min(size, chunk_remain);
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if (size >= 4) {
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if (host->data->flags & MMC_DATA_READ)
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*(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
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else
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writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
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size = 4;
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} else if (size >= 2) {
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if (host->data->flags & MMC_DATA_READ)
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*(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
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else
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writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
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size = 2;
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} else {
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if (host->data->flags & MMC_DATA_READ)
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*(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
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else
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writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
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size = 1;
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}
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buffer += size;
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chunk_remain -= size;
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blksize -= size;
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host->offset += size;
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host->remain -= size;
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bytes += size;
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host->size -= size;
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while (size) {
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*buffer = data & 0xFF;
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buffer++;
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data >>= 8;
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size--;
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}
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if (host->remain == 0) {
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sdhci_kunmap_sg(host);
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if (sdhci_next_sg(host) == 0) {
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DBG("PIO transfer: %d bytes\n", bytes);
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BUG_ON(blksize != 0);
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return;
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}
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buffer = sdhci_kmap_sg(host);
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@ -252,38 +234,137 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
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}
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sdhci_kunmap_sg(host);
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}
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DBG("PIO transfer: %d bytes\n", bytes);
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static void sdhci_write_block_pio(struct sdhci_host *host)
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{
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int blksize, chunk_remain;
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u32 data;
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char *buffer;
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int bytes, size;
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DBG("PIO writing\n");
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blksize = host->data->blksz;
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chunk_remain = 4;
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data = 0;
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bytes = 0;
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buffer = sdhci_kmap_sg(host) + host->offset;
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while (blksize) {
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size = min(host->size, host->remain);
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size = min(size, chunk_remain);
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chunk_remain -= size;
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blksize -= size;
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host->offset += size;
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host->remain -= size;
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host->size -= size;
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while (size) {
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data >>= 8;
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data |= (u32)*buffer << 24;
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buffer++;
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size--;
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}
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if (chunk_remain == 0) {
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writel(data, host->ioaddr + SDHCI_BUFFER);
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chunk_remain = min(blksize, 4);
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}
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if (host->remain == 0) {
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sdhci_kunmap_sg(host);
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if (sdhci_next_sg(host) == 0) {
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BUG_ON(blksize != 0);
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return;
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}
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buffer = sdhci_kmap_sg(host);
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}
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}
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sdhci_kunmap_sg(host);
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}
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static void sdhci_transfer_pio(struct sdhci_host *host)
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{
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u32 mask;
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BUG_ON(!host->data);
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if (host->size == 0)
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return;
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if (host->data->flags & MMC_DATA_READ)
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mask = SDHCI_DATA_AVAILABLE;
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else
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mask = SDHCI_SPACE_AVAILABLE;
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while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
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if (host->data->flags & MMC_DATA_READ)
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sdhci_read_block_pio(host);
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else
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sdhci_write_block_pio(host);
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if (host->size == 0)
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break;
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BUG_ON(host->num_sg == 0);
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}
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DBG("PIO transfer complete.\n");
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}
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static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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{
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u16 mode;
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u8 count;
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unsigned target_timeout, current_timeout;
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WARN_ON(host->data);
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if (data == NULL) {
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writew(0, host->ioaddr + SDHCI_TRANSFER_MODE);
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if (data == NULL)
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return;
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}
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DBG("blksz %04x blks %04x flags %08x\n",
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data->blksz, data->blocks, data->flags);
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DBG("tsac %d ms nsac %d clk\n",
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data->timeout_ns / 1000000, data->timeout_clks);
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mode = SDHCI_TRNS_BLK_CNT_EN;
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if (data->blocks > 1)
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mode |= SDHCI_TRNS_MULTI;
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if (data->flags & MMC_DATA_READ)
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mode |= SDHCI_TRNS_READ;
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if (host->flags & SDHCI_USE_DMA)
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mode |= SDHCI_TRNS_DMA;
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/* Sanity checks */
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BUG_ON(data->blksz * data->blocks > 524288);
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BUG_ON(data->blksz > host->max_block);
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BUG_ON(data->blocks > 65535);
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writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
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/* timeout in us */
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target_timeout = data->timeout_ns / 1000 +
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data->timeout_clks / host->clock;
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writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
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writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
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/*
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* Figure out needed cycles.
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* We do this in steps in order to fit inside a 32 bit int.
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* The first step is the minimum timeout, which will have a
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* minimum resolution of 6 bits:
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* (1) 2^13*1000 > 2^22,
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* (2) host->timeout_clk < 2^16
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* =>
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* (1) / (2) > 2^6
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*/
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count = 0;
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current_timeout = (1 << 13) * 1000 / host->timeout_clk;
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while (current_timeout < target_timeout) {
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count++;
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current_timeout <<= 1;
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if (count >= 0xF)
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break;
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}
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if (count >= 0xF) {
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printk(KERN_WARNING "%s: Too large timeout requested!\n",
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mmc_hostname(host->mmc));
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count = 0xE;
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}
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writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
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if (host->flags & SDHCI_USE_DMA) {
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int count;
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@ -302,12 +383,37 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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host->offset = 0;
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host->remain = host->cur_sg->length;
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}
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
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host->ioaddr + SDHCI_BLOCK_SIZE);
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writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
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}
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static void sdhci_set_transfer_mode(struct sdhci_host *host,
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struct mmc_data *data)
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{
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u16 mode;
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WARN_ON(host->data);
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if (data == NULL)
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return;
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mode = SDHCI_TRNS_BLK_CNT_EN;
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if (data->blocks > 1)
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mode |= SDHCI_TRNS_MULTI;
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if (data->flags & MMC_DATA_READ)
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mode |= SDHCI_TRNS_READ;
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if (host->flags & SDHCI_USE_DMA)
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mode |= SDHCI_TRNS_DMA;
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writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
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}
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|
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static void sdhci_finish_data(struct sdhci_host *host)
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{
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struct mmc_data *data;
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u32 intmask;
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u16 blocks;
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BUG_ON(!host->data);
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|
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@ -318,14 +424,6 @@ static void sdhci_finish_data(struct sdhci_host *host)
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if (host->flags & SDHCI_USE_DMA) {
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pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
|
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(data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
|
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} else {
|
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intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
|
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intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
|
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writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
|
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|
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intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
|
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intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
|
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writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
|
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}
|
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|
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/*
|
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|
|
@ -371,27 +469,38 @@ static void sdhci_finish_data(struct sdhci_host *host)
|
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static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
|
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{
|
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int flags;
|
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u32 present;
|
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unsigned long max_jiffies;
|
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u32 mask;
|
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unsigned long timeout;
|
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|
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WARN_ON(host->cmd);
|
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|
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DBG("Sending cmd (%x)\n", cmd->opcode);
|
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|
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/* Wait max 10 ms */
|
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max_jiffies = jiffies + (HZ + 99)/100;
|
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do {
|
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if (time_after(jiffies, max_jiffies)) {
|
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timeout = 10;
|
||||
|
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mask = SDHCI_CMD_INHIBIT;
|
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if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
|
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mask |= SDHCI_DATA_INHIBIT;
|
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|
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/* We shouldn't wait for data inihibit for stop commands, even
|
||||
though they might use busy signaling */
|
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if (host->mrq->data && (cmd == host->mrq->data->stop))
|
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mask &= ~SDHCI_DATA_INHIBIT;
|
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|
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while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
|
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if (timeout == 0) {
|
||||
printk(KERN_ERR "%s: Controller never released "
|
||||
"inhibit bits. Please report this to "
|
||||
"inhibit bit(s). Please report this to "
|
||||
BUGMAIL ".\n", mmc_hostname(host->mmc));
|
||||
sdhci_dumpregs(host);
|
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cmd->error = MMC_ERR_FAILED;
|
||||
tasklet_schedule(&host->finish_tasklet);
|
||||
return;
|
||||
}
|
||||
present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
|
||||
} while (present & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT));
|
||||
timeout--;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
mod_timer(&host->timer, jiffies + 10 * HZ);
|
||||
|
||||
|
|
@ -401,6 +510,8 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
|
|||
|
||||
writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
|
||||
|
||||
sdhci_set_transfer_mode(host, cmd->data);
|
||||
|
||||
if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
|
||||
printk(KERN_ERR "%s: Unsupported response type! "
|
||||
"Please report this to " BUGMAIL ".\n",
|
||||
|
|
@ -456,31 +567,9 @@ static void sdhci_finish_command(struct sdhci_host *host)
|
|||
|
||||
DBG("Ending cmd (%x)\n", host->cmd->opcode);
|
||||
|
||||
if (host->cmd->data) {
|
||||
u32 intmask;
|
||||
|
||||
if (host->cmd->data)
|
||||
host->data = host->cmd->data;
|
||||
|
||||
if (!(host->flags & SDHCI_USE_DMA)) {
|
||||
/*
|
||||
* Don't enable the interrupts until now to make sure we
|
||||
* get stable handling of the FIFO.
|
||||
*/
|
||||
intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
|
||||
intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
|
||||
writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
|
||||
|
||||
intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
|
||||
intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
|
||||
writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
|
||||
|
||||
/*
|
||||
* The buffer interrupts are to unreliable so we
|
||||
* start the transfer immediatly.
|
||||
*/
|
||||
sdhci_transfer_pio(host);
|
||||
}
|
||||
} else
|
||||
else
|
||||
tasklet_schedule(&host->finish_tasklet);
|
||||
|
||||
host->cmd = NULL;
|
||||
|
|
@ -490,7 +579,7 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
|
|||
{
|
||||
int div;
|
||||
u16 clk;
|
||||
unsigned long max_jiffies;
|
||||
unsigned long timeout;
|
||||
|
||||
if (clock == host->clock)
|
||||
return;
|
||||
|
|
@ -511,17 +600,19 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
|
|||
writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
|
||||
|
||||
/* Wait max 10 ms */
|
||||
max_jiffies = jiffies + (HZ + 99)/100;
|
||||
do {
|
||||
if (time_after(jiffies, max_jiffies)) {
|
||||
timeout = 10;
|
||||
while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
|
||||
& SDHCI_CLOCK_INT_STABLE)) {
|
||||
if (timeout == 0) {
|
||||
printk(KERN_ERR "%s: Internal clock never stabilised. "
|
||||
"Please report this to " BUGMAIL ".\n",
|
||||
mmc_hostname(host->mmc));
|
||||
sdhci_dumpregs(host);
|
||||
return;
|
||||
}
|
||||
clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL);
|
||||
} while (!(clk & SDHCI_CLOCK_INT_STABLE));
|
||||
timeout--;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
clk |= SDHCI_CLOCK_CARD_EN;
|
||||
writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
|
||||
|
|
@ -530,6 +621,46 @@ out:
|
|||
host->clock = clock;
|
||||
}
|
||||
|
||||
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
|
||||
{
|
||||
u8 pwr;
|
||||
|
||||
if (host->power == power)
|
||||
return;
|
||||
|
||||
writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
|
||||
|
||||
if (power == (unsigned short)-1)
|
||||
goto out;
|
||||
|
||||
pwr = SDHCI_POWER_ON;
|
||||
|
||||
switch (power) {
|
||||
case MMC_VDD_170:
|
||||
case MMC_VDD_180:
|
||||
case MMC_VDD_190:
|
||||
pwr |= SDHCI_POWER_180;
|
||||
break;
|
||||
case MMC_VDD_290:
|
||||
case MMC_VDD_300:
|
||||
case MMC_VDD_310:
|
||||
pwr |= SDHCI_POWER_300;
|
||||
break;
|
||||
case MMC_VDD_320:
|
||||
case MMC_VDD_330:
|
||||
case MMC_VDD_340:
|
||||
pwr |= SDHCI_POWER_330;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
|
||||
|
||||
out:
|
||||
host->power = power;
|
||||
}
|
||||
|
||||
/*****************************************************************************\
|
||||
* *
|
||||
* MMC callbacks *
|
||||
|
|
@ -576,17 +707,15 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
*/
|
||||
if (ios->power_mode == MMC_POWER_OFF) {
|
||||
writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
sdhci_init(host);
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
}
|
||||
|
||||
sdhci_set_clock(host, ios->clock);
|
||||
|
||||
if (ios->power_mode == MMC_POWER_OFF)
|
||||
writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
|
||||
sdhci_set_power(host, -1);
|
||||
else
|
||||
writeb(0xFF, host->ioaddr + SDHCI_POWER_CONTROL);
|
||||
sdhci_set_power(host, ios->vdd);
|
||||
|
||||
ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
|
||||
if (ios->bus_width == MMC_BUS_WIDTH_4)
|
||||
|
|
@ -793,7 +922,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
|
|||
if (host->data->error != MMC_ERR_NONE)
|
||||
sdhci_finish_data(host);
|
||||
else {
|
||||
if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
|
||||
if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
|
||||
sdhci_transfer_pio(host);
|
||||
|
||||
if (intmask & SDHCI_INT_DATA_END)
|
||||
|
|
@ -818,50 +947,44 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
|
|||
|
||||
DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
|
||||
|
||||
if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
|
||||
if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
|
||||
writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
|
||||
host->ioaddr + SDHCI_INT_STATUS);
|
||||
tasklet_schedule(&host->card_tasklet);
|
||||
}
|
||||
|
||||
intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
|
||||
|
||||
if (intmask & SDHCI_INT_CMD_MASK) {
|
||||
sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
|
||||
|
||||
writel(intmask & SDHCI_INT_CMD_MASK,
|
||||
host->ioaddr + SDHCI_INT_STATUS);
|
||||
sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
|
||||
}
|
||||
|
||||
if (intmask & SDHCI_INT_DATA_MASK) {
|
||||
sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
|
||||
|
||||
writel(intmask & SDHCI_INT_DATA_MASK,
|
||||
host->ioaddr + SDHCI_INT_STATUS);
|
||||
sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
|
||||
}
|
||||
|
||||
intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
|
||||
|
||||
if (intmask & SDHCI_INT_CARD_INT) {
|
||||
printk(KERN_ERR "%s: Unexpected card interrupt. Please "
|
||||
"report this to " BUGMAIL ".\n",
|
||||
mmc_hostname(host->mmc));
|
||||
sdhci_dumpregs(host);
|
||||
}
|
||||
|
||||
if (intmask & SDHCI_INT_BUS_POWER) {
|
||||
printk(KERN_ERR "%s: Unexpected bus power interrupt. Please "
|
||||
"report this to " BUGMAIL ".\n",
|
||||
printk(KERN_ERR "%s: Card is consuming too much power!\n",
|
||||
mmc_hostname(host->mmc));
|
||||
sdhci_dumpregs(host);
|
||||
writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
|
||||
}
|
||||
|
||||
if (intmask & SDHCI_INT_ACMD12ERR) {
|
||||
printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please "
|
||||
intmask &= SDHCI_INT_BUS_POWER;
|
||||
|
||||
if (intmask) {
|
||||
printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
|
||||
"report this to " BUGMAIL ".\n",
|
||||
mmc_hostname(host->mmc));
|
||||
mmc_hostname(host->mmc), intmask);
|
||||
sdhci_dumpregs(host);
|
||||
|
||||
writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
|
||||
}
|
||||
|
||||
if (intmask)
|
||||
writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
|
||||
}
|
||||
|
||||
result = IRQ_HANDLED;
|
||||
|
||||
|
|
@ -954,6 +1077,7 @@ static int sdhci_resume (struct pci_dev *pdev)
|
|||
static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
|
||||
{
|
||||
int ret;
|
||||
unsigned int version;
|
||||
struct sdhci_chip *chip;
|
||||
struct mmc_host *mmc;
|
||||
struct sdhci_host *host;
|
||||
|
|
@ -985,6 +1109,16 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
|
||||
printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
|
||||
printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
|
||||
if (!mmc)
|
||||
return -ENOMEM;
|
||||
|
|
@ -1012,9 +1146,30 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
|
|||
goto release;
|
||||
}
|
||||
|
||||
sdhci_reset(host, SDHCI_RESET_ALL);
|
||||
|
||||
version = readw(host->ioaddr + SDHCI_HOST_VERSION);
|
||||
version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
|
||||
if (version != 0) {
|
||||
printk(KERN_ERR "%s: Unknown controller version (%d). "
|
||||
"Cowardly refusing to continue.\n", host->slot_descr,
|
||||
version);
|
||||
ret = -ENODEV;
|
||||
goto unmap;
|
||||
}
|
||||
|
||||
caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
|
||||
|
||||
if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
|
||||
if (debug_nodma)
|
||||
DBG("DMA forced off\n");
|
||||
else if (debug_forcedma) {
|
||||
DBG("DMA forced on\n");
|
||||
host->flags |= SDHCI_USE_DMA;
|
||||
} else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
|
||||
DBG("Controller doesn't have DMA interface\n");
|
||||
else if (!(caps & SDHCI_CAN_DO_DMA))
|
||||
DBG("Controller doesn't have DMA capability\n");
|
||||
else
|
||||
host->flags |= SDHCI_USE_DMA;
|
||||
|
||||
if (host->flags & SDHCI_USE_DMA) {
|
||||
|
|
@ -1030,18 +1185,59 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
|
|||
else /* XXX: Hack to get MMC layer to avoid highmem */
|
||||
pdev->dma_mask = 0;
|
||||
|
||||
host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
|
||||
host->max_clk =
|
||||
(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
|
||||
if (host->max_clk == 0) {
|
||||
printk(KERN_ERR "%s: Hardware doesn't specify base clock "
|
||||
"frequency.\n", host->slot_descr);
|
||||
ret = -ENODEV;
|
||||
goto unmap;
|
||||
}
|
||||
host->max_clk *= 1000000;
|
||||
|
||||
host->timeout_clk =
|
||||
(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
|
||||
if (host->timeout_clk == 0) {
|
||||
printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
|
||||
"frequency.\n", host->slot_descr);
|
||||
ret = -ENODEV;
|
||||
goto unmap;
|
||||
}
|
||||
if (caps & SDHCI_TIMEOUT_CLK_UNIT)
|
||||
host->timeout_clk *= 1000;
|
||||
|
||||
host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
|
||||
if (host->max_block >= 3) {
|
||||
printk(KERN_ERR "%s: Invalid maximum block size.\n",
|
||||
host->slot_descr);
|
||||
ret = -ENODEV;
|
||||
goto unmap;
|
||||
}
|
||||
host->max_block = 512 << host->max_block;
|
||||
|
||||
/*
|
||||
* Set host parameters.
|
||||
*/
|
||||
mmc->ops = &sdhci_ops;
|
||||
mmc->f_min = host->max_clk / 256;
|
||||
mmc->f_max = host->max_clk;
|
||||
mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
|
||||
mmc->caps = MMC_CAP_4_BIT_DATA;
|
||||
|
||||
mmc->ocr_avail = 0;
|
||||
if (caps & SDHCI_CAN_VDD_330)
|
||||
mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
|
||||
else if (caps & SDHCI_CAN_VDD_300)
|
||||
mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
|
||||
else if (caps & SDHCI_CAN_VDD_180)
|
||||
mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
|
||||
|
||||
if (mmc->ocr_avail == 0) {
|
||||
printk(KERN_ERR "%s: Hardware doesn't report any "
|
||||
"support voltages.\n", host->slot_descr);
|
||||
ret = -ENODEV;
|
||||
goto unmap;
|
||||
}
|
||||
|
||||
spin_lock_init(&host->lock);
|
||||
|
||||
/*
|
||||
|
|
@ -1054,10 +1250,10 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
|
|||
mmc->max_phys_segs = 16;
|
||||
|
||||
/*
|
||||
* Maximum number of sectors in one transfer. Limited by sector
|
||||
* count register.
|
||||
* Maximum number of sectors in one transfer. Limited by DMA boundary
|
||||
* size (512KiB), which means (512 KiB/512=) 1024 entries.
|
||||
*/
|
||||
mmc->max_sectors = 0x3FFF;
|
||||
mmc->max_sectors = 1024;
|
||||
|
||||
/*
|
||||
* Maximum segment size. Could be one segment with the maximum number
|
||||
|
|
@ -1078,7 +1274,7 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
|
|||
ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
|
||||
host->slot_descr, host);
|
||||
if (ret)
|
||||
goto unmap;
|
||||
goto untasklet;
|
||||
|
||||
sdhci_init(host);
|
||||
|
||||
|
|
@ -1097,10 +1293,10 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
|
|||
|
||||
return 0;
|
||||
|
||||
unmap:
|
||||
untasklet:
|
||||
tasklet_kill(&host->card_tasklet);
|
||||
tasklet_kill(&host->finish_tasklet);
|
||||
|
||||
unmap:
|
||||
iounmap(host->ioaddr);
|
||||
release:
|
||||
pci_release_region(pdev, host->bar);
|
||||
|
|
@ -1144,13 +1340,18 @@ static int __devinit sdhci_probe(struct pci_dev *pdev,
|
|||
const struct pci_device_id *ent)
|
||||
{
|
||||
int ret, i;
|
||||
u8 slots;
|
||||
u8 slots, rev;
|
||||
struct sdhci_chip *chip;
|
||||
|
||||
BUG_ON(pdev == NULL);
|
||||
BUG_ON(ent == NULL);
|
||||
|
||||
DBG("found at %s\n", pci_name(pdev));
|
||||
pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
|
||||
|
||||
printk(KERN_INFO DRIVER_NAME
|
||||
": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
|
||||
pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
|
||||
(int)rev);
|
||||
|
||||
ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
|
||||
if (ret)
|
||||
|
|
@ -1173,6 +1374,10 @@ static int __devinit sdhci_probe(struct pci_dev *pdev,
|
|||
}
|
||||
|
||||
chip->pdev = pdev;
|
||||
chip->quirks = ent->driver_data;
|
||||
|
||||
if (debug_quirks)
|
||||
chip->quirks = debug_quirks;
|
||||
|
||||
chip->num_slots = slots;
|
||||
pci_set_drvdata(pdev, chip);
|
||||
|
|
@ -1251,7 +1456,15 @@ static void __exit sdhci_drv_exit(void)
|
|||
module_init(sdhci_drv_init);
|
||||
module_exit(sdhci_drv_exit);
|
||||
|
||||
module_param(debug_nodma, uint, 0444);
|
||||
module_param(debug_forcedma, uint, 0444);
|
||||
module_param(debug_quirks, uint, 0444);
|
||||
|
||||
MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
|
||||
MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
|
||||
MODULE_VERSION(DRIVER_VERSION);
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
|
||||
MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
|
||||
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
|
||||
|
|
|
|||
|
|
@ -12,6 +12,10 @@
|
|||
* PCI registers
|
||||
*/
|
||||
|
||||
#define PCI_SDHCI_IFPIO 0x00
|
||||
#define PCI_SDHCI_IFDMA 0x01
|
||||
#define PCI_SDHCI_IFVENDOR 0x02
|
||||
|
||||
#define PCI_SLOT_INFO 0x40 /* 8 bits */
|
||||
#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
|
||||
#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
|
||||
|
|
@ -23,6 +27,7 @@
|
|||
#define SDHCI_DMA_ADDRESS 0x00
|
||||
|
||||
#define SDHCI_BLOCK_SIZE 0x04
|
||||
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
|
||||
|
||||
#define SDHCI_BLOCK_COUNT 0x06
|
||||
|
||||
|
|
@ -67,6 +72,10 @@
|
|||
#define SDHCI_CTRL_4BITBUS 0x02
|
||||
|
||||
#define SDHCI_POWER_CONTROL 0x29
|
||||
#define SDHCI_POWER_ON 0x01
|
||||
#define SDHCI_POWER_180 0x0A
|
||||
#define SDHCI_POWER_300 0x0C
|
||||
#define SDHCI_POWER_330 0x0E
|
||||
|
||||
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
|
||||
|
||||
|
|
@ -91,8 +100,8 @@
|
|||
#define SDHCI_INT_RESPONSE 0x00000001
|
||||
#define SDHCI_INT_DATA_END 0x00000002
|
||||
#define SDHCI_INT_DMA_END 0x00000008
|
||||
#define SDHCI_INT_BUF_EMPTY 0x00000010
|
||||
#define SDHCI_INT_BUF_FULL 0x00000020
|
||||
#define SDHCI_INT_SPACE_AVAIL 0x00000010
|
||||
#define SDHCI_INT_DATA_AVAIL 0x00000020
|
||||
#define SDHCI_INT_CARD_INSERT 0x00000040
|
||||
#define SDHCI_INT_CARD_REMOVE 0x00000080
|
||||
#define SDHCI_INT_CARD_INT 0x00000100
|
||||
|
|
@ -112,7 +121,7 @@
|
|||
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
|
||||
SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
|
||||
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
|
||||
SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL | \
|
||||
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
|
||||
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
|
||||
SDHCI_INT_DATA_END_BIT)
|
||||
|
||||
|
|
@ -121,9 +130,17 @@
|
|||
/* 3E-3F reserved */
|
||||
|
||||
#define SDHCI_CAPABILITIES 0x40
|
||||
#define SDHCI_CAN_DO_DMA 0x00400000
|
||||
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
|
||||
#define SDHCI_TIMEOUT_CLK_SHIFT 0
|
||||
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
|
||||
#define SDHCI_CLOCK_BASE_MASK 0x00003F00
|
||||
#define SDHCI_CLOCK_BASE_SHIFT 8
|
||||
#define SDHCI_MAX_BLOCK_MASK 0x00030000
|
||||
#define SDHCI_MAX_BLOCK_SHIFT 16
|
||||
#define SDHCI_CAN_DO_DMA 0x00400000
|
||||
#define SDHCI_CAN_VDD_330 0x01000000
|
||||
#define SDHCI_CAN_VDD_300 0x02000000
|
||||
#define SDHCI_CAN_VDD_180 0x04000000
|
||||
|
||||
/* 44-47 reserved for more caps */
|
||||
|
||||
|
|
@ -136,6 +153,10 @@
|
|||
#define SDHCI_SLOT_INT_STATUS 0xFC
|
||||
|
||||
#define SDHCI_HOST_VERSION 0xFE
|
||||
#define SDHCI_VENDOR_VER_MASK 0xFF00
|
||||
#define SDHCI_VENDOR_VER_SHIFT 8
|
||||
#define SDHCI_SPEC_VER_MASK 0x00FF
|
||||
#define SDHCI_SPEC_VER_SHIFT 0
|
||||
|
||||
struct sdhci_chip;
|
||||
|
||||
|
|
@ -149,8 +170,11 @@ struct sdhci_host {
|
|||
#define SDHCI_USE_DMA (1<<0)
|
||||
|
||||
unsigned int max_clk; /* Max possible freq (MHz) */
|
||||
unsigned int timeout_clk; /* Timeout freq (KHz) */
|
||||
unsigned int max_block; /* Max block size (bytes) */
|
||||
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
unsigned short power; /* Current voltage */
|
||||
|
||||
struct mmc_request *mrq; /* Current request */
|
||||
struct mmc_command *cmd; /* Current command */
|
||||
|
|
@ -180,6 +204,8 @@ struct sdhci_host {
|
|||
struct sdhci_chip {
|
||||
struct pci_dev *pdev;
|
||||
|
||||
unsigned long quirks;
|
||||
|
||||
int num_slots; /* Slots on controller */
|
||||
struct sdhci_host *hosts[0]; /* Pointers to hosts */
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue