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dmaengine, async_tx: add a "no channel switch" allocator
Channel switching is problematic for some dmaengine drivers as the architecture precludes separating the ->prep from ->submit. In these cases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify the async_tx allocator to only return channels that support all of the required asynchronous operations. For example MD_RAID456=y selects support for asynchronous xor, xor validate, pq, pq validate, and memcpy. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=y any channel with all these capabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to quickly locate compatible channels with the guarantee that dependency chains will remain on one channel. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=n async_tx_find_channel() may select channels that lead to operation chains that need to cross channel boundaries using the async_tx channel switch capability. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
parent
0403e38277
commit
138f4c359d
4 changed files with 57 additions and 1 deletions
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@ -81,6 +81,10 @@ async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
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struct dma_device *device = chan->device;
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struct dma_device *device = chan->device;
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struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
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struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
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#ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
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BUG();
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#endif
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/* first check to see if we can still append to depend_tx */
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/* first check to see if we can still append to depend_tx */
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spin_lock_bh(&depend_tx->lock);
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spin_lock_bh(&depend_tx->lock);
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if (depend_tx->parent && depend_tx->chan == tx->chan) {
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if (depend_tx->parent && depend_tx->chan == tx->chan) {
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@ -17,11 +17,15 @@ if DMADEVICES
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comment "DMA Devices"
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comment "DMA Devices"
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config ASYNC_TX_DISABLE_CHANNEL_SWITCH
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bool
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config INTEL_IOATDMA
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config INTEL_IOATDMA
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tristate "Intel I/OAT DMA support"
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tristate "Intel I/OAT DMA support"
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depends on PCI && X86
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depends on PCI && X86
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select DMA_ENGINE
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select DMA_ENGINE
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select DCA
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select DCA
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select ASYNC_TX_DISABLE_CHANNEL_SWITCH
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help
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help
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Enable support for the Intel(R) I/OAT DMA engine present
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Enable support for the Intel(R) I/OAT DMA engine present
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in recent Intel Xeon chipsets.
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in recent Intel Xeon chipsets.
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@ -608,6 +608,40 @@ void dmaengine_put(void)
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}
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}
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EXPORT_SYMBOL(dmaengine_put);
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EXPORT_SYMBOL(dmaengine_put);
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static bool device_has_all_tx_types(struct dma_device *device)
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{
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/* A device that satisfies this test has channels that will never cause
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* an async_tx channel switch event as all possible operation types can
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* be handled.
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*/
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#ifdef CONFIG_ASYNC_TX_DMA
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if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
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return false;
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#endif
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#if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
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if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
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return false;
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#endif
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#if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
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if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
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return false;
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#endif
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#if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
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if (!dma_has_cap(DMA_XOR, device->cap_mask))
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return false;
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#endif
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#if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
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if (!dma_has_cap(DMA_PQ, device->cap_mask))
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return false;
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#endif
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return true;
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}
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static int get_dma_id(struct dma_device *device)
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static int get_dma_id(struct dma_device *device)
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{
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{
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int rc;
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int rc;
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@ -665,6 +699,12 @@ int dma_async_device_register(struct dma_device *device)
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BUG_ON(!device->device_issue_pending);
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BUG_ON(!device->device_issue_pending);
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BUG_ON(!device->dev);
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BUG_ON(!device->dev);
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/* note: this only matters in the
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* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y case
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*/
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if (device_has_all_tx_types(device))
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dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
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idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
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idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
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if (!idr_ref)
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if (!idr_ref)
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return -ENOMEM;
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return -ENOMEM;
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@ -48,6 +48,9 @@ enum dma_status {
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/**
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/**
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* enum dma_transaction_type - DMA transaction types/indexes
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* enum dma_transaction_type - DMA transaction types/indexes
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*
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* Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
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* automatically set as dma devices are registered.
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*/
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*/
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enum dma_transaction_type {
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enum dma_transaction_type {
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DMA_MEMCPY,
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DMA_MEMCPY,
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@ -61,6 +64,7 @@ enum dma_transaction_type {
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DMA_MEMCPY_CRC32C,
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DMA_MEMCPY_CRC32C,
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DMA_INTERRUPT,
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DMA_INTERRUPT,
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DMA_PRIVATE,
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DMA_PRIVATE,
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DMA_ASYNC_TX,
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DMA_SLAVE,
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DMA_SLAVE,
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};
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};
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@ -396,7 +400,11 @@ static inline void net_dmaengine_put(void)
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#ifdef CONFIG_ASYNC_TX_DMA
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#ifdef CONFIG_ASYNC_TX_DMA
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#define async_dmaengine_get() dmaengine_get()
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#define async_dmaengine_get() dmaengine_get()
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#define async_dmaengine_put() dmaengine_put()
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#define async_dmaengine_put() dmaengine_put()
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#ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
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#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
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#else
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#define async_dma_find_channel(type) dma_find_channel(type)
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#define async_dma_find_channel(type) dma_find_channel(type)
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#endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */
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#else
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#else
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static inline void async_dmaengine_get(void)
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static inline void async_dmaengine_get(void)
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{
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{
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@ -409,7 +417,7 @@ async_dma_find_channel(enum dma_transaction_type type)
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{
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{
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return NULL;
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return NULL;
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}
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}
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#endif
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#endif /* CONFIG_ASYNC_TX_DMA */
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dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
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dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
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void *dest, void *src, size_t len);
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void *dest, void *src, size_t len);
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