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perf_counter: Add P6 PMU support
Add basic P6 PMU support. The P6 uses the EVNTSEL0 EN bit to enable/disable both its counters. We use this for the global enable/disable, and clear all config bits (except EN) to disable individual counters. Actual ia32 hardware doesn't support lfence, so use a locked op without side-effect to implement a full barrier. perf stat and perf record seem to function correctly. [a.p.zijlstra@chello.nl: cleanups and complete the enable/disable code] Signed-off-by: Vince Weaver <vince@deater.net> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <Pine.LNX.4.64.0907081718450.2715@pianoman.cluster.toy> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Vince Weaver
Ingo Molnar
parent
9590b7ba3f
commit
11d1578f94
2 changed files with 220 additions and 15 deletions
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@ -65,6 +65,44 @@ static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
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.enabled = 1,
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};
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/*
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* Not sure about some of these
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*/
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static const u64 p6_perfmon_event_map[] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0000,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x0000,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
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[PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
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};
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static u64 p6_pmu_event_map(int event)
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{
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return p6_perfmon_event_map[event];
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}
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static u64 p6_pmu_raw_event(u64 event)
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{
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#define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
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#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
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#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
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#define P6_EVNTSEL_INV_MASK 0x00800000ULL
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#define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL
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#define P6_EVNTSEL_MASK \
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(P6_EVNTSEL_EVENT_MASK | \
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P6_EVNTSEL_UNIT_MASK | \
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P6_EVNTSEL_EDGE_MASK | \
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P6_EVNTSEL_INV_MASK | \
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P6_EVNTSEL_COUNTER_MASK)
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return event & P6_EVNTSEL_MASK;
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}
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/*
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* Intel PerfMon v3. Used on Core2 and later.
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*/
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@ -726,6 +764,23 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
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return 0;
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}
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static void p6_pmu_disable_all(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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unsigned long val;
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if (!cpuc->enabled)
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return;
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cpuc->enabled = 0;
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barrier();
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/* p6 only has one enable register */
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rdmsrl(MSR_P6_EVNTSEL0, val);
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_P6_EVNTSEL0, val);
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}
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static void intel_pmu_disable_all(void)
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{
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
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@ -767,6 +822,23 @@ void hw_perf_disable(void)
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return x86_pmu.disable_all();
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}
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static void p6_pmu_enable_all(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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unsigned long val;
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if (cpuc->enabled)
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return;
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cpuc->enabled = 1;
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barrier();
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/* p6 only has one enable register */
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rdmsrl(MSR_P6_EVNTSEL0, val);
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_P6_EVNTSEL0, val);
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}
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static void intel_pmu_enable_all(void)
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{
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
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@ -819,16 +891,13 @@ static inline void intel_pmu_ack_status(u64 ack)
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static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
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{
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int err;
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err = checking_wrmsrl(hwc->config_base + idx,
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(void)checking_wrmsrl(hwc->config_base + idx,
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hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
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}
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static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
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{
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int err;
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err = checking_wrmsrl(hwc->config_base + idx,
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hwc->config);
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(void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
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}
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static inline void
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@ -836,13 +905,24 @@ intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
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{
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int idx = __idx - X86_PMC_IDX_FIXED;
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u64 ctrl_val, mask;
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int err;
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mask = 0xfULL << (idx * 4);
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rdmsrl(hwc->config_base, ctrl_val);
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ctrl_val &= ~mask;
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err = checking_wrmsrl(hwc->config_base, ctrl_val);
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(void)checking_wrmsrl(hwc->config_base, ctrl_val);
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}
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static inline void
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p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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unsigned long val = ARCH_PERFMON_EVENTSEL0_ENABLE;
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if (!cpuc->enabled)
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val = 0;
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(void)checking_wrmsrl(hwc->config_base + idx, val);
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}
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static inline void
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@ -943,6 +1023,17 @@ intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
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err = checking_wrmsrl(hwc->config_base, ctrl_val);
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}
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static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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if (cpuc->enabled)
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x86_pmu_enable_counter(hwc, idx);
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else
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x86_pmu_disable_counter(hwc, idx);
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}
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static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
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{
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
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@ -1176,6 +1267,49 @@ static void intel_pmu_reset(void)
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local_irq_restore(flags);
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}
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static int p6_pmu_handle_irq(struct pt_regs *regs)
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{
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struct perf_sample_data data;
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struct cpu_hw_counters *cpuc;
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struct perf_counter *counter;
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struct hw_perf_counter *hwc;
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int idx, handled = 0;
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u64 val;
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data.regs = regs;
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data.addr = 0;
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cpuc = &__get_cpu_var(cpu_hw_counters);
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for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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if (!test_bit(idx, cpuc->active_mask))
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continue;
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counter = cpuc->counters[idx];
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hwc = &counter->hw;
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val = x86_perf_counter_update(counter, hwc, idx);
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if (val & (1ULL << (x86_pmu.counter_bits - 1)))
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continue;
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/*
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* counter overflow
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*/
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handled = 1;
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data.period = counter->hw.last_period;
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if (!x86_perf_counter_set_period(counter, hwc, idx))
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continue;
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if (perf_counter_overflow(counter, 1, &data))
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p6_pmu_disable_counter(hwc, idx);
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}
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if (handled)
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inc_irq_stat(apic_perf_irqs);
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return handled;
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}
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/*
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* This handler is triggered by the local APIC, so the APIC IRQ handling
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@ -1185,14 +1319,13 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
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{
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struct perf_sample_data data;
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struct cpu_hw_counters *cpuc;
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int bit, cpu, loops;
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int bit, loops;
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u64 ack, status;
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data.regs = regs;
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data.addr = 0;
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cpu = smp_processor_id();
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cpuc = &per_cpu(cpu_hw_counters, cpu);
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cpuc = &__get_cpu_var(cpu_hw_counters);
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perf_disable();
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status = intel_pmu_get_status();
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@ -1249,14 +1382,13 @@ static int amd_pmu_handle_irq(struct pt_regs *regs)
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struct cpu_hw_counters *cpuc;
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struct perf_counter *counter;
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struct hw_perf_counter *hwc;
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int cpu, idx, handled = 0;
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int idx, handled = 0;
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u64 val;
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data.regs = regs;
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data.addr = 0;
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cpu = smp_processor_id();
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cpuc = &per_cpu(cpu_hw_counters, cpu);
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cpuc = &__get_cpu_var(cpu_hw_counters);
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for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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if (!test_bit(idx, cpuc->active_mask))
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@ -1353,6 +1485,32 @@ static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
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.priority = 1
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};
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static struct x86_pmu p6_pmu = {
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.name = "p6",
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.handle_irq = p6_pmu_handle_irq,
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.disable_all = p6_pmu_disable_all,
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.enable_all = p6_pmu_enable_all,
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.enable = p6_pmu_enable_counter,
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.disable = p6_pmu_disable_counter,
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.eventsel = MSR_P6_EVNTSEL0,
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.perfctr = MSR_P6_PERFCTR0,
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.event_map = p6_pmu_event_map,
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.raw_event = p6_pmu_raw_event,
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.max_events = ARRAY_SIZE(p6_perfmon_event_map),
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.max_period = (1ULL << 31) - 1,
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.version = 0,
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.num_counters = 2,
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/*
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* Counters have 40 bits implemented. However they are designed such
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* that bits [32-39] are sign extensions of bit 31. As such the
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* effective width of a counter for P6-like PMU is 32 bits only.
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*
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* See IA-32 Intel Architecture Software developer manual Vol 3B
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*/
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.counter_bits = 32,
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.counter_mask = (1ULL << 32) - 1,
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};
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static struct x86_pmu intel_pmu = {
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.name = "Intel",
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.handle_irq = intel_pmu_handle_irq,
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@ -1392,6 +1550,41 @@ static struct x86_pmu amd_pmu = {
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.max_period = (1ULL << 47) - 1,
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};
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static int p6_pmu_init(void)
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{
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int high, low;
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switch (boot_cpu_data.x86_model) {
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case 1:
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case 3: /* Pentium Pro */
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case 5:
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case 6: /* Pentium II */
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case 7:
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case 8:
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case 11: /* Pentium III */
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break;
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case 9:
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case 13:
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/* for Pentium M, we need to check if PMU exist */
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rdmsr(MSR_IA32_MISC_ENABLE, low, high);
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if (low & MSR_IA32_MISC_ENABLE_EMON)
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break;
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default:
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pr_cont("unsupported p6 CPU model %d ",
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boot_cpu_data.x86_model);
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return -ENODEV;
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}
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if (!cpu_has_apic) {
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pr_info("no Local APIC, try rebooting with lapic");
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return -ENODEV;
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}
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x86_pmu = p6_pmu;
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return 0;
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}
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static int intel_pmu_init(void)
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{
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union cpuid10_edx edx;
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@ -1400,8 +1593,14 @@ static int intel_pmu_init(void)
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unsigned int ebx;
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int version;
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if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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/* check for P6 processor family */
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if (boot_cpu_data.x86 == 6) {
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return p6_pmu_init();
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} else {
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return -ENODEV;
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}
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}
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/*
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* Check whether the Architectural PerfMon supports
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@ -1,7 +1,13 @@
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#ifndef _PERF_PERF_H
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#define _PERF_PERF_H
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#if defined(__x86_64__) || defined(__i386__)
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#if defined(__i386__)
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#include "../../arch/x86/include/asm/unistd.h"
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#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#endif
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#if defined(__x86_64__)
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#include "../../arch/x86/include/asm/unistd.h"
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#define rmb() asm volatile("lfence" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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